From 3ad3978aaa9ee09487fe808631e40911425f5aab Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Apr 2019 01:52:31 +0100 Subject: [PATCH] use Mux in UnbufferedPipeline2 --- src/add/singlepipe.py | 8 ++--- src/add/test_buf_pipe.py | 70 ++++++++++++++++++++++++++-------------- 2 files changed, 49 insertions(+), 29 deletions(-) diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 06ef732b..bb1426a0 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -847,11 +847,9 @@ class UnbufferedPipeline2(ControlBase): self.m.d.comb += self.p._o_ready.eq(~buf_full) self.m.d.sync += buf_full.eq(~self.n.i_ready_test & \ (p_i_valid | buf_full)) - with self.m.If(buf_full): - self.m.d.comb += eq(self.n.o_data, buf) - with self.m.Else(): - self.m.d.comb += eq(self.n.o_data, - self.stage.process(self.p.i_data)) + + odata = Mux(buf_full, buf, self.stage.process(self.p.i_data)) + self.m.d.comb += eq(self.n.o_data, odata) self.m.d.sync += eq(buf, self.n.o_data) return self.m diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index 7933df34..d81e7f10 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -666,19 +666,27 @@ class ExampleUnBufDelayedPipe(BufferedPipeline): return m ###################################################################### -# Test 14 +# Test 15 ###################################################################### -class ExampleBufPipe3(ControlBase): - """ Example of how to do delayed pipeline, where the stage signals - whether it is ready. - """ +class ExampleBufModeAdd1Pipe(BufferedPipeline2): + + def __init__(self): + stage = ExampleStageCls() + BufferedPipeline2.__init__(self, stage) + + +###################################################################### +# Test 16 +###################################################################### + +class ExampleBufModeUnBufPipe(ControlBase): def elaborate(self, platform): m = ControlBase._elaborate(self, platform) - pipe1 = ExampleBufDelayedPipe() - pipe2 = ExampleBufPipe() + pipe1 = ExampleBufModeAdd1Pipe() + pipe2 = ExampleBufAdd1Pipe() m.submodules.pipe1 = pipe1 m.submodules.pipe2 = pipe2 @@ -688,27 +696,30 @@ class ExampleBufPipe3(ControlBase): return m ###################################################################### -# Test 15 +# Test 17 ###################################################################### -class ExampleBufModeAdd1Pipe(BufferedPipeline2): +class ExampleUnBufAdd1Pipe2(UnbufferedPipeline2): def __init__(self): stage = ExampleStageCls() - BufferedPipeline2.__init__(self, stage) + UnbufferedPipeline2.__init__(self, stage) ###################################################################### -# Test 16 +# Test 998 ###################################################################### -class ExampleBufModeUnBufPipe(ControlBase): +class ExampleBufPipe3(ControlBase): + """ Example of how to do delayed pipeline, where the stage signals + whether it is ready. + """ def elaborate(self, platform): m = ControlBase._elaborate(self, platform) - pipe1 = ExampleBufModeAdd1Pipe() - pipe2 = ExampleBufAdd1Pipe() + pipe1 = ExampleBufDelayedPipe() + pipe2 = ExampleBufPipe() m.submodules.pipe1 = pipe1 m.submodules.pipe2 = pipe2 @@ -717,7 +728,6 @@ class ExampleBufModeUnBufPipe(ControlBase): return m - ###################################################################### # Test 999 - XXX FAILS # http://bugs.libre-riscv.org/show_bug.cgi?id=57 @@ -884,7 +894,7 @@ if __name__ == '__main__': with open("test_unbufpipe13.il", "w") as f: f.write(vl) - print ("test 15)") + print ("test 15") dut = ExampleBufModeAdd1Pipe() data = data_chain1() test = Test5(dut, test12_resultfn, data=data) @@ -896,28 +906,40 @@ if __name__ == '__main__': with open("test_bufunbuf15.il", "w") as f: f.write(vl) - print ("test 14") - dut = ExampleBufPipe3() + print ("test 16") + dut = ExampleBufModeUnBufPipe() data = data_chain1() test = Test5(dut, test9_resultfn, data=data) - run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd") + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd") ports = [dut.p.i_valid, dut.n.i_ready, dut.n.o_valid, dut.p.o_ready] + \ [dut.p.i_data] + [dut.n.o_data] vl = rtlil.convert(dut, ports=ports) - with open("test_bufpipe14.il", "w") as f: + with open("test_bufunbuf16.il", "w") as f: f.write(vl) - print ("test 16)") - dut = ExampleBufModeUnBufPipe() + print ("test 17") + dut = ExampleUnBufAdd1Pipe2() + data = data_chain1() + test = Test5(dut, test12_resultfn, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd") + ports = [dut.p.i_valid, dut.n.i_ready, + dut.n.o_valid, dut.p.o_ready] + \ + [dut.p.i_data] + [dut.n.o_data] + vl = rtlil.convert(dut, ports=ports) + with open("test_unbufpipe17.il", "w") as f: + f.write(vl) + + print ("test 998 (fails, bug)") + dut = ExampleBufPipe3() data = data_chain1() test = Test5(dut, test9_resultfn, data=data) - run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd") + run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd") ports = [dut.p.i_valid, dut.n.i_ready, dut.n.o_valid, dut.p.o_ready] + \ [dut.p.i_data] + [dut.n.o_data] vl = rtlil.convert(dut, ports=ports) - with open("test_bufunbuf16.il", "w") as f: + with open("test_bufpipe14.il", "w") as f: f.write(vl) print ("test 999 (expected to fail, which is a bug)") -- 2.30.2