From 42d693196f2060bc45c929691baf583f86f19ec4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 14:42:41 +0100 Subject: [PATCH] add PLL clock loop-back into CPU --- libresoc/core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libresoc/core.py b/libresoc/core.py index 178ebe8..7ebbbdd 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -186,6 +186,7 @@ class LibreSoC(CPU): self.platform = platform self.variant = variant self.reset = Signal() + self.clk = ClockSignal() irq_en = "noirq" not in variant @@ -236,7 +237,7 @@ class LibreSoC(CPU): self.cpu_params = dict( # Clock / Reset - i_clk = ClockSignal(), + i_clk = self.clk, i_rst = ResetSignal() | self.reset, # Monitoring / Debugging -- 2.30.2