From 4561335e764d0aaf501044076e48610dad45855c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 7 Feb 2024 13:25:40 +0000 Subject: [PATCH] bug 1055: missed out fpload/store-shift instructions for ls004 (doh) --- openpower/isa/fploadshift.mdwn | 154 +++++++++++++++++++++ openpower/isa/fpstoreshift.mdwn | 236 ++++++++++++++++++++++++++++++++ 2 files changed, 390 insertions(+) create mode 100644 openpower/isa/fploadshift.mdwn create mode 100644 openpower/isa/fpstoreshift.mdwn diff --git a/openpower/isa/fploadshift.mdwn b/openpower/isa/fploadshift.mdwn new file mode 100644 index 00000000..58119e25 --- /dev/null +++ b/openpower/isa/fploadshift.mdwn @@ -0,0 +1,154 @@ + + +# Load Floating-Point Single Indexed Shifted + +X-Form + +* lfssx FRT,RA,RB,SH + +Pseudo-code: + + EA <- (RA|0) + (RB)<<(SH+1) + FRT <- DOUBLE(MEM(EA, 4)) + +Description: + + Let the effective address (EA) be the sum of (RA|0) with + the contents of register RB shifted by (SH+1). + + The word in storage addressed by EA is interpreted as + a floating-point single-precision operand. This word is + converted to floating-point double format (see + page 138) and placed into register FRT. + +Special Registers Altered: + + None + +# Load Floating-Point Single with Update Indexed Shifted + +X-Form + +* lfsusx FRT,RA,RB,SH + +Pseudo-code: + + EA <- (RA) + (RB)<<(SH+1) + FRT <- DOUBLE(MEM(EA, 4)) + RA <- EA + +Description: + + Let the effective address (EA) be the sum of the contents of + register RB shifted by (SH+1), and the contents of register RA. + + The word in storage addressed by EA is interpreted as + a floating-point single-precision operand. This word is + converted to floating-point double format (see + page 138) and placed into register FRT. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Load Floating-Point Double Indexed Shifted + +X-Form + +* lfdsx FRT,RA,RB,SH + +Pseudo-code: + + EA <- (RA|0) + (RB)<<(SH+1) + FRT <- MEM(EA, 8) + +Description: + + Let the effective address (EA) be the sum of (RA|0) with + the contents of register RB shifted by (SH+1). + + The doubleword in storage addressed by EA is loaded + into register FRT. + +Special Registers Altered: + + None + +# Load Floating-Point Double with Update Indexed + +X-Form + +* lfdusx FRT,RA,RB,SH + +Pseudo-code: + + EA <- (RA) + (RB)<<(SH+1) + FRT <- MEM(EA, 8) + RA <- EA + +Description: + + Let the effective address (EA) be the sum of the contents of + register RB shifted by (SH+1), and the contents of register RA. + + The doubleword in storage addressed by EA is loaded + into register FRT. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Load Floating-Point as Integer Word Algebraic Indexed Shifted + +X-Form + +* lfiwasx FRT,RA,RB,SH + +Pseudo-code: + + EA <- (RA|0) + (RB)<<(SH+1) + FRT <- EXTS(MEM(EA, 4)) + +Description: + + Let the effective address (EA) be the sum of (RA|0) with + the contents of register RB shifted by (SH+1). + + The word in storage addressed by EA is loaded into + FRT [32:63]. FRT [0:31] are filled with a copy of bit 0 of the + loaded word. + +Special Registers Altered: + + None + +# Load Floating-Point as Integer Word Zero Indexed Shifted + +X-Form + +* lfiwzsx FRT,RA,RB + +Pseudo-code: + + EA <- (RA|0) + (RB)<<(SH+1) + FRT <- [0]*32 || MEM(EA, 4) + +Description: + + Let the effective address (EA) be the sum of (RA|0) with + the contents of register RB shifted by (SH+1). + + The word in storage addressed by EA is loaded into + FRT [32:63]. FRT [0:31] are set to 0. + +Special Registers Altered: + + None diff --git a/openpower/isa/fpstoreshift.mdwn b/openpower/isa/fpstoreshift.mdwn new file mode 100644 index 00000000..16bce78c --- /dev/null +++ b/openpower/isa/fpstoreshift.mdwn @@ -0,0 +1,236 @@ + + +# Store Floating-Point Single + +D-Form + +* stfs FRS,D(RA) + +Pseudo-code: + + EA <- (RA|0) + EXTS(D) + MEM(EA, 4)<- SINGLE( (FRS) ) + +Description: + + Let the effective address (EA) be the sum (RA|0)+D. + + The contents of register FRS are converted to single + format (see page 142) and stored into the word in stor- + age addressed by EA. + +Special Registers Altered: + + None + +# Store Floating-Point Single Indexed + +X-Form + +* stfsx FRS,RA,RB + +Pseudo-code: + + EA <- (RA|0) + (RB) + MEM(EA, 4)<- SINGLE( (FRS) ) + +Description: + + Let the effective address (EA) be the sum (RA|0)+(RB). + + The contents of register FRS are converted to single + format (see page 142) and stored into the word in stor- + age addressed by EA. + +Special Registers Altered: + + None + +# Store Floating-Point Single with Update + +D-Form + +* stfsu FRS,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + MEM(EA, 4)<- SINGLE( (FRS) ) + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA) +D. + + The contents of register FRS are converted to single + format (see page 142) and stored into the word in stor- + age addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Floating-Point Single with Update Indexed + +X-Form + +* stfsux FRS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 4)<- SINGLE( (FRS) ) + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA) +(RB). + + The contents of register FRS are converted to single + format (see page 142) and stored into the word in stor- + age addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Floating-Point Double + +D-Form + +* stfd FRS,D(RA) + +Pseudo-code: + + EA <- (RA|0) + EXTS(D) + MEM(EA, 8)<- (FRS) + +Description: + + Let the effective address (EA) be the sum (RA|0)+D. + + The contents of register FRS are stored into the dou- + bleword in storage addressed by EA. + +Special Registers Altered: + + None + +# Store Floating-Point Double Indexed + +X-Form + +* stfdx FRS,RA,RB + +Pseudo-code: + + EA <- (RA|0) + (RB) + MEM(EA, 8)<- (FRS) + +Description: + + Let the effective address (EA) be the sum (RA|0)+(RB). + + The contents of register FRS are stored into the dou- + bleword in storage addressed by EA. + +Special Registers Altered: + + None + +# Store Floating-Point Double with Update + +D-Form + +* stfdu FRS,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + MEM(EA, 8)<- (FRS) + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+D. + + The contents of register FRS are stored into the dou- + bleword in storage addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Floating-Point Double with Update Indexed + +X-Form + +* stfdux FRS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + MEM(EA, 8)<- (FRS) + RA <- EA + +Description: + + Let the effective address (EA) be the sum (RA)+(RB). + + The contents of register FRS are stored into the dou- + bleword in storage addressed by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + +Special Registers Altered: + + None + +# Store Floating-Point as Integer Word Indexed + +X-Form + +* stfiwx FRS,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 8)<- (FRS)[32:63] + +Description: + + Let the effective address (EA) be the sum (RA|0)+(RB). + + (FRS)[32:63] are stored, without conversion, into the word + in storage addressed by EA. + + If the contents of register FRS were produced, either + directly or indirectly, by a Load Floating-Point Single + instruction, a single-precision Arithmetic instruction, or + frsp, then the value stored is undefined. (The contents + of register FRS are produced directly by such an + instruction if FRS is the target register for the instruc- + tion. The contents of register FRS are produced indi- + rectly by such an instruction if FRS is the final target + register of a sequence of one or more Floating-Point + Move instructions, with the input to the sequence hav- + ing been produced directly by such an instruction.) + +Special Registers Altered: + + None -- 2.30.2