From 52a3d3916b905d3e9e7e7e606c77aa9ab58a4f3d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Mar 2019 03:22:31 +0000 Subject: [PATCH] move ids to member variable --- src/add/nmigen_add_experiment.py | 6 +++--- src/add/unit_test_single.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index deabc682..d829e0ec 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -1430,11 +1430,11 @@ class FPADD(FPID): * id_wid: an identifier that is sync-connected to the input * single_cycle: True indicates each stage to complete in 1 clock """ - FPID.__init__(self, id_wid) self.width = width self.id_wid = id_wid self.single_cycle = single_cycle + self.ids = FPID(id_wid) self.in_a = FPOp(width) self.in_b = FPOp(width) self.out_z = FPOp(width) @@ -1465,8 +1465,8 @@ class FPADD(FPID): ab = FPADDBase(self.width, self.id_wid, self.single_cycle) ab = self.add_state(ab) - ab.setup(m, a, b, getb.out_decode, self.in_mid, - self.out_z, self.out_mid) + ab.setup(m, a, b, getb.out_decode, self.ids.in_mid, + self.out_z, self.ids.out_mid) #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z, # ab.out_mid, self.out_mid)) diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py index 19f7cd65..e14d4f92 100644 --- a/src/add/unit_test_single.py +++ b/src/add/unit_test_single.py @@ -37,7 +37,7 @@ def match(x, y): ) def get_case(dut, a, b, mid): - yield dut.in_mid.eq(mid) + yield dut.ids.in_mid.eq(mid) yield dut.in_a.v.eq(a) yield dut.in_a.stb.eq(1) yield @@ -66,7 +66,7 @@ def get_case(dut, a, b, mid): yield continue out_z = yield dut.out_z.v - out_mid = yield dut.out_mid + out_mid = yield dut.ids.out_mid yield dut.out_z.ack.eq(0) yield break -- 2.30.2