From 57837140b31cbba0b38f5dd7fcd9dd9102ee63bf Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 09:05:31 +0000
Subject: [PATCH] move classes to before use

---
 src/add/nmigen_add_experiment.py | 56 +++++++++++++++++---------------
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index cbac766f..8e3ace3a 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -187,6 +187,36 @@ class FPGetOp(FPState):
             m.d.sync += self.in_op.ack.eq(1)
 
 
+class FPNumBase2Ops:
+
+    def __init__(self, width, id_wid, m_extra=True):
+        self.a = FPNumBase(width, m_extra)
+        self.b = FPNumBase(width, m_extra)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+    def ports(self):
+        return [self.a, self.b, self.mid]
+
+
+class FPADDBaseData:
+
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.a  = Signal(width)
+        self.b  = Signal(width)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+    def ports(self):
+        return [self.a, self.b, self.mid]
+
+
 class FPGet2OpMod(Trigger):
     def __init__(self, width, id_wid):
         Trigger.__init__(self)
@@ -255,17 +285,6 @@ class FPGet2Op(FPState):
             m.d.sync += self.mod.ack.eq(1)
 
 
-class FPNumBase2Ops:
-
-    def __init__(self, width, id_wid, m_extra=True):
-        self.a = FPNumBase(width, m_extra)
-        self.b = FPNumBase(width, m_extra)
-        self.mid = Signal(id_wid, reset_less=True)
-
-    def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
-
-
 class FPSCData:
 
     def __init__(self, width, id_wid):
@@ -1609,21 +1628,6 @@ class FPPutZIdx(FPState):
         with m.Else():
             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
 
-class FPADDBaseData:
-
-    def __init__(self, width, id_wid):
-        self.width = width
-        self.id_wid = id_wid
-        self.a  = Signal(width)
-        self.b  = Signal(width)
-        self.mid = Signal(id_wid, reset_less=True)
-
-    def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
-
-    def ports(self):
-        return [self.a, self.b, self.mid]
-
 class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOp(width)
-- 
2.30.2