From 5fbf78c99195d89a54a943311061b3a04faf3ccd Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 4 Aug 2020 11:29:28 +0200 Subject: [PATCH] Default SEL to 1's if SEL=0 (fixes #43) --- gram/frontend/wishbone.py | 6 ++++++ gram/test/test_frontend_wishbone.py | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/gram/frontend/wishbone.py b/gram/frontend/wishbone.py index 44856bd..658bf9d 100644 --- a/gram/frontend/wishbone.py +++ b/gram/frontend/wishbone.py @@ -37,6 +37,12 @@ class gramWishbone(Peripheral, Elaboratable): ratio_bitmask = Repl(1, log2_int(self.ratio)) + sel = Signal.like(self.bus.sel) + with m.If(self.bus.sel == 0): + m.d.comb += sel.eq(Repl(1, sel.width)) + with m.Else(): + m.d.comb += sel.eq(self.bus.sel) + with m.Switch(self.bus.adr & ratio_bitmask): for i in range(self.ratio): with m.Case(i): diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py index ff07cc0..d016d60 100644 --- a/gram/test/test_frontend_wishbone.py +++ b/gram/test/test_frontend_wishbone.py @@ -308,3 +308,27 @@ class GramWishboneTestCase(FHDLTestCase): ackCallback=selfirstdword) runSimulation(dut, process, "test_frontend_wishbone.vcd") + + def test_sel_empty(self): + core = FakeGramCore() + native_port = core.crossbar.get_native_port() + dut = gramWishbone(core, data_width=32, granularity=8) + + def process(): + # Initialize native port + yield native_port.cmd.ready.eq(0) + yield native_port.wdata.ready.eq(0) + yield native_port.rdata.valid.eq(0) + + def selfirstdword(bus, native_port): + self.assertEqual((yield native_port.wdata.we), 0xF) + + yield from self.write_request(bus=dut.bus, + native_port=native_port, + adr=0, + sel=0, + value=0xAAAAAAAA, + timeout=128, + ackCallback=selfirstdword) + + runSimulation(dut, process, "test_frontend_wishbone.vcd") -- 2.30.2