From 633b7c510ac505fa17d0c318b44aa0625867c03c Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 15 Jul 2022 14:07:06 +0200 Subject: [PATCH] optionally add ECLKBRIDGECS to ECP5CRG --- src/ecp5_crg.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py index 403ff7d..11bb8a9 100644 --- a/src/ecp5_crg.py +++ b/src/ecp5_crg.py @@ -170,7 +170,7 @@ class PLL(Elaboratable): class ECP5CRG(Elaboratable): def __init__(self, sys_clk_freq=100e6, dram_clk_freq=None, - pod_bits=25, sync_bits=26): + pod_bits=25, sync_bits=26, need_bridge=False): """when dram_clk_freq=None, a dramsync domain is still created but it is an alias of sync domain. likewise the 2x """ @@ -178,6 +178,7 @@ class ECP5CRG(Elaboratable): self.dram_clk_freq = dram_clk_freq self.pod_bits = pod_bits # for init domain self.sync_bits = sync_bits # for all other domains + self.need_bridge = need_bridge # insert ECLKBRIDGECS assert pod_bits <= sync_bits, \ "power-on-delay bits %d should " \ " be less than sync_bits %d" % (pod_bits, sync_bits) @@ -204,7 +205,18 @@ class ECP5CRG(Elaboratable): # create PLL clocks pll.create_clkout(ClockSignal(cd2x_ub), 2*freq) if esyncb: - m.submodules["%s_eclksyncb" % cd] = Instance("ECLKSYNCB", + if self.need_bridge: + sys2x_clk_ecsout = Signal() + m.submodules["%s_eclkbridgecs" % cd] = Instance("ECLKBRIDGECS", + i_CLK0 = ClockSignal(cd2x_ub), + i_SEL = 0, + o_ECSOUT = sys2x_clk_ecsout) + m.submodules["%s_eclksyncb" % cd] = Instance("ECLKSYNCB", + i_ECLKI = sys2x_clk_ecsout, + i_STOP = 0, + o_ECLKO = ClockSignal(cd2x)) + else: + m.submodules["%s_eclksyncb" % cd] = Instance("ECLKSYNCB", i_ECLKI = ClockSignal(cd2x_ub), i_STOP = 0, o_ECLKO = ClockSignal(cd2x)) -- 2.30.2