From 6e288c0869759266eef57a8aa7ddb62d3a1d2692 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 11:30:42 +0000 Subject: [PATCH] sort out clock names in experiments10_verilog --- experiments10_verilog/add.py | 26 ++++++++++++++------- experiments10_verilog/coriolis2/settings.py | 2 +- experiments10_verilog/doDesign.py | 8 ++++--- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py index 909607a..6514cde 100644 --- a/experiments10_verilog/add.py +++ b/experiments10_verilog/add.py @@ -199,8 +199,23 @@ class ADD(Elaboratable): m.d.comb += self.core.jtag.bus.tdi.eq(self.jtag_tdi) m.d.comb += self.core.jtag.bus.tms.eq(self.jtag_tms) m.d.comb += self.core.jtag.bus.tck.eq(self.jtag_tck) + + # dummy to get a sync clk + #x = Signal() + #m.d.sync += x.eq(~x ^ self.a) + return m + def ports(self): + return [#ClockSignal(), ResetSignal(), + self.a, self.b, self.f, + self.a0, self.a1, # PLL mode + self.pll_test, self.pll_vco, # PLL test + self.jtag_tck, + self.jtag_tms, + self.jtag_tdo, + self.jtag_tdi] + def create_verilog(dut, ports, test_name): vl = verilog.convert(dut, name=test_name, ports=ports) @@ -208,11 +223,6 @@ def create_verilog(dut, ports, test_name): f.write(vl) if __name__ == "__main__": - alu = DomainRenamer("sys")(ADD(width=4)) - create_verilog(alu, [alu.a, alu.b, alu.f, - alu.a0, alu.a1, # PLL mode - alu.pll_test, alu.pll_vco, # PLL test - alu.jtag_tck, - alu.jtag_tms, - alu.jtag_tdo, - alu.jtag_tdi], "add") + #alu = DomainRenamer("sys")(ADD(width=4)) + alu = (ADD(width=4)) + create_verilog(alu, alu.ports(), "add") diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py index 22e72f5..f8ab1ea 100644 --- a/experiments10_verilog/coriolis2/settings.py +++ b/experiments10_verilog/coriolis2/settings.py @@ -108,7 +108,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) af = CRL.AllianceFramework.get() env = af.getEnvironment() - env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) + env.setCLOCK( '^clk$|^ck|^jtag_tck$' ) env.setPOWER( 'vdd' ) env.setGROUND( 'vss' ) env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py index 74a5be1..54a8a32 100644 --- a/experiments10_verilog/doDesign.py +++ b/experiments10_verilog/doDesign.py @@ -48,7 +48,7 @@ def scriptMain ( **kw ): , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms' , 'jtag_tms' ) , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo' , 'jtag_tdo' ) , (IoPin.EAST , None, 'ground_0' , 'vss' ) - , (IoPin.EAST , None, 'p_sys_clk' , 'sys_clk' , 'sys_clk' ) + , (IoPin.EAST , None, 'p_sys_clk' , 'clk' , 'clk' ) , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck' , 'jtag_tck' ) , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi' , 'jtag_tdi' ) , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) @@ -59,10 +59,12 @@ def scriptMain ( **kw ): , (IoPin.NORTH, None, 'p_pll_test' , 'pll_test' , 'pll_test' ) , (IoPin.NORTH, None, 'a0' , 'a0' , 'a0' ) , (IoPin.NORTH, None, 'a1' , 'a1' , 'a1' ) - , (IoPin.NORTH, None, 'p_sys_rst' , 'sys_rst' , 'sys_rst' ) + , (IoPin.NORTH, None, 'p_sys_rst' , 'rst' , 'rst' ) , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' ) , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' ) , (IoPin.WEST , None, 'power_1' , 'vdd' ) + , (IoPin.WEST , None, 'coresync_clk', 'coresync_clk', 'coresync_clk' ) + #, (IoPin.WEST , None, 'coresync_rst', 'coresync_rst', 'coresync_rst' ) , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' ) , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' ) , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' ) @@ -87,7 +89,7 @@ def scriptMain ( **kw ): adderConf.chipConf.ioPadGauge = 'niolib' adderConf.useHTree('coresync_clk') adderConf.useHTree('jtag_tck_from_pad') - adderConf.useHTree('sys_clk_from_pad') + adderConf.useHTree('clk_from_pad') adderConf.coreSize = ( l(coreSize), l(coreSize) ) adderConf.chipSize = ( l(coreSize+3500), l(coreSize+3500) ) adderToChip = CoreToChip( adderConf ) -- 2.30.2