From 6f31d65eb4433b66d64fcf924f2c0eb3cb4b9b3b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 14:50:19 +0100 Subject: [PATCH] try setting domain to "CPU" --- libresoc/core.py | 2 +- ls180soc.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index 7ebbbdd..6706a21 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -186,7 +186,7 @@ class LibreSoC(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.clk = ClockSignal() + self.clk = ClockSignal("cpu") irq_en = "noirq" not in variant diff --git a/ls180soc.py b/ls180soc.py index 5f91d69..7836add 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -433,8 +433,8 @@ class LibreSoCSim(SoCCore): self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag - clk = ClockSignal() - self.comb += clk.eq(self.cpu.pllclk_o) # PLL out into cpu + cpu_clk = ClockDomain("cpu") + self.comb += cpu_clk.eq(self.cpu.pllclk_o) # PLL out into cpu #ram_init = [] -- 2.30.2