From 72494e3b94a8cb7715c42f038212315f50681f63 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Apr 2019 06:21:18 +0100 Subject: [PATCH] add extra FIFOTest pipe to test 21, to see if sync-delays occur --- src/add/test_buf_pipe.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index 7155c908..37f2b31f 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -790,12 +790,14 @@ class ExampleFIFOPassThruPipe1(ControlBase): m = ControlBase.elaborate(self, platform) pipe1 = FIFOTest16() - pipe2 = ExamplePassAdd1Pipe() + pipe2 = FIFOTest16() + pipe3 = ExamplePassAdd1Pipe() m.submodules.pipe1 = pipe1 m.submodules.pipe2 = pipe2 + m.submodules.pipe3 = pipe3 - m.d.comb += self.connect([pipe1, pipe2]) + m.d.comb += self.connect([pipe1, pipe2, pipe3]) return m -- 2.30.2