From 725400f06b2346bd523169b698ecfa85a7b20c03 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Thu, 7 Apr 2022 15:23:13 -0500 Subject: [PATCH] Backport litedram 05ed5bf59d31029d3f91c5a348cdd539a150631b phy/ecp5ddrphy: simplify using new get_sys_phase. --- gram/common.py | 2 ++ gram/phy/ecp5ddrphy.py | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/gram/common.py b/gram/common.py index 7c5f449..c8bc6ad 100644 --- a/gram/common.py +++ b/gram/common.py @@ -54,6 +54,8 @@ def get_cl_cw(memtype, tck): def get_sys_latency(nphases, cas_latency): return math.ceil(cas_latency/nphases) +def get_sys_phase(nphases, sys_latency, cas_latency): + return sys_latency*nphases - cas_latency def get_sys_phases(nphases, sys_latency, cas_latency): dat_phase = sys_latency*nphases - cas_latency diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 513582e..585031d 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -154,8 +154,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable): cl, cwl = get_cl_cw("DDR3", tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) - rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) - wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) + rdphase = get_sys_phase(nphases, cl_sys_latency, cl) + wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl) self.settings = PhySettings( phytype="ECP5DDRPHY", memtype="DDR3", @@ -165,11 +165,11 @@ class ECP5DDRPHY(Peripheral, Elaboratable): nphases=nphases, rdphase=rdphase, wrphase=wrphase, - rdcmdphase=rdcmdphase, - wrcmdphase=wrcmdphase, + rdcmdphase = (rdphase - 1)%nphases, + wrcmdphase = (wrphase - 1)%nphases, cl=cl, cwl=cwl, - read_latency=2 + cl_sys_latency + 2 + log2_int(4//nphases) + 4, + read_latency = cl_sys_latency + 10, write_latency=cwl_sys_latency ) -- 2.30.2