From 74d880336ad3c358cb83d4a74657da229dc68f38 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 May 2021 17:25:35 +0000
Subject: [PATCH] rename cell to "real_pll" to avoid conflict with cell also
 named "pll"

---
 experiments9/coriolis2/settings.py            |   10 +-
 .../full_core_4_4ksram_libresoc.v             | 7892 ++++++++---------
 2 files changed, 3951 insertions(+), 3951 deletions(-)

diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py
index 6d111f0..2dc3588 100644
--- a/experiments9/coriolis2/settings.py
+++ b/experiments9/coriolis2/settings.py
@@ -29,15 +29,15 @@ def createPLLBlackbox ():
     rootlib  = db.getRootLibrary()
     lib      = rootlib.getLibrary( 'pll' )
     pllName = 'pll'
-    pll     = lib.getCell( sramName )
+    pll     = lib.getCell( pllName )
     if not pll:
         raise ErrorMessage( 1, 'settings.createPLLBlackBox(): '
                                 'PLL Cell "{}" not found.' \
-                               .format(sramName) )
-    sram.setAbstractedSupply( True )
-    blackboxName = 'pll'
+                               .format(pllName) )
+    pll.setAbstractedSupply( True )
+    blackboxName = 'real_pll'
     cell     = Cell.create( lib, blackboxName )
-    instance = Instance.create( cell, 'pll', pll )
+    instance = Instance.create( cell, 'real_pll', pll )
     state    = af.getCatalog().getState( blackboxName, True )
     state.setCell( cell )
     state.setLogical( True )
diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
index de16d04..f347544 100644
--- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v
+++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
@@ -39286,829 +39286,831 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core" *)
 (* generator = "nMigen" *)
-module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, \exc_o_$signal , core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fast3, core_fast3_ok, core_fasto1, core_fasto2, core_fasto3, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core__sv_pred_sz, core_core__sv_pred_dz, core_core__sv_saturate, core_core__SV_Ptype, core_core_msr, core_core_cia, core_core_svstate, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, core_msr, raw_insn_i, bigendian_i, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
+module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, exc_o_happened, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fast3, core_fast3_ok, core_fasto1, core_fasto2, core_fasto3, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core__sv_pred_sz, core_core__sv_pred_dz, core_core__sv_saturate, core_core__SV_Ptype, core_core_msr, core_core_cia, core_core_svstate, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, core_core_exc_alignment, core_core_exc_instr_fault, core_core_exc_invalid, core_core_exc_badtree, core_core_exc_perm_error, core_core_exc_rc_error, core_core_exc_segment_fault, core_core_exc_happened, core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, core_msr, raw_insn_i, bigendian_i, \wen$3 , \data_i$4 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$5 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
   reg \initial  = 0;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1000 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1002 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
   wire \$1004 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1007 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1011 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1013 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1018 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1021 ;
+  wire [6:0] \$1007 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1023 ;
+  wire \$1009 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1026 ;
+  wire \$1012 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1030 ;
+  wire \$1016 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1032 ;
+  wire \$1018 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1041 ;
+  wire \$1027 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1044 ;
+  wire [6:0] \$1030 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1046 ;
+  wire \$1032 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1049 ;
+  wire \$1035 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1053 ;
+  wire \$1039 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1055 ;
+  wire \$1041 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1059 ;
+  wire \$1045 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1062 ;
+  wire [6:0] \$1048 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1064 ;
+  wire \$1050 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1067 ;
+  wire \$1053 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1071 ;
+  wire \$1057 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1073 ;
+  wire \$1059 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1081 ;
+  wire \$1067 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1084 ;
+  wire [6:0] \$1070 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1086 ;
+  wire \$1072 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1089 ;
+  wire \$1075 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1093 ;
+  wire \$1079 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1095 ;
+  wire \$1081 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1101 ;
+  wire \$1087 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1104 ;
+  wire [6:0] \$1090 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1106 ;
+  wire \$1092 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1109 ;
+  wire \$1095 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1113 ;
+  wire \$1099 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1115 ;
+  wire \$1101 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1121 ;
+  wire \$1107 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1124 ;
+  wire [6:0] \$1110 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1126 ;
+  wire \$1112 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1129 ;
+  wire \$1115 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1133 ;
+  wire \$1119 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1135 ;
+  wire \$1121 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1140 ;
+  wire \$1126 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1143 ;
+  wire [6:0] \$1129 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1145 ;
+  wire \$1131 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1148 ;
+  wire \$1134 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1152 ;
+  wire \$1138 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1154 ;
+  wire \$1140 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1158 ;
+  wire \$1144 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1161 ;
+  wire [6:0] \$1147 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1163 ;
+  wire \$1149 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1166 ;
+  wire \$1152 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1169 ;
+  wire \$1155 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1171 ;
+  wire \$1157 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1174 ;
+  wire \$1160 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [6:0] \$1177 ;
+  wire [6:0] \$1163 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [64:0] \$1179 ;
+  wire [64:0] \$1165 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [63:0] \$1180 ;
+  wire [63:0] \$1166 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [63:0] \$1182 ;
+  wire [63:0] \$1168 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [63:0] \$1184 ;
+  wire [63:0] \$1170 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [63:0] \$1186 ;
+  wire [63:0] \$1172 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [63:0] \$1188 ;
+  wire [63:0] \$1174 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *)
-  wire [64:0] \$1190 ;
+  wire [64:0] \$1176 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [64:0] \$1192 ;
+  wire [64:0] \$1178 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [64:0] \$1194 ;
+  wire [64:0] \$1180 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [64:0] \$1196 ;
+  wire [64:0] \$1182 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1198 ;
+  wire [6:0] \$1184 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$1199 ;
+  wire [6:0] \$1185 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$1201 ;
+  wire [6:0] \$1187 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1203 ;
+  wire [6:0] \$1189 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1205 ;
+  wire [6:0] \$1191 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$1207 ;
+  wire [6:0] \$1193 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$1209 ;
+  wire [6:0] \$1195 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1211 ;
+  wire [6:0] \$1197 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1213 ;
+  wire [6:0] \$1199 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$1215 ;
+  wire [6:0] \$1201 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$1217 ;
+  wire \$1203 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$1219 ;
+  wire \$1205 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$1221 ;
+  wire \$1207 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$1223 ;
+  wire \$1209 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$1225 ;
+  wire \$1211 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$1227 ;
+  wire \$1213 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$1229 ;
+  wire \$1215 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$1231 ;
+  wire \$1217 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$1233 ;
+  wire \$1219 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1235 ;
+  wire \$1221 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1237 ;
+  wire \$1223 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1240 ;
+  wire \$1226 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1243 ;
+  wire \$1229 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1245 ;
+  wire \$1231 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1248 ;
+  wire \$1234 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [7:0] \$1251 ;
+  wire [7:0] \$1237 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1253 ;
+  wire \$1239 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1255 ;
+  wire \$1241 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1257 ;
+  wire \$1243 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1259 ;
+  wire \$1245 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1261 ;
+  wire \$1247 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1263 ;
+  wire \$1249 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$1265 ;
+  wire \$1251 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1268 ;
+  wire \$1254 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1271 ;
+  wire \$1257 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1273 ;
+  wire \$1259 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1276 ;
+  wire \$1262 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
-  wire [7:0] \$1279 ;
+  wire [7:0] \$1265 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
-  wire [255:0] \$1281 ;
+  wire [255:0] \$1267 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [255:0] \$1283 ;
+  wire [255:0] \$1269 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1285 ;
+  wire \$1271 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1288 ;
+  wire \$1274 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1291 ;
+  wire \$1277 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1293 ;
+  wire \$1279 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
-  wire \$1296 ;
+  wire \$1282 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
-  wire [7:0] \$1299 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [3:0] \$1391 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [3:0] \$1393 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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+  wire [255:0] \$1388 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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-  wire \$1654 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
-  wire \$1657 ;
+  wire \$1643 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1661 ;
+  wire \$1647 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$1663 ;
+  wire \$1649 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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+  wire \$1654 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [2:0] \$1671 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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+  wire \$1665 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [2:0] \$1719 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$1721 ;
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire \$171 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire [14:0] \$172 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
-  wire [2:0] \$1751 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [63:0] \$1753 ;
+  wire [63:0] \$1739 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [63:0] \$1755 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [63:0] \$1761 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire \$175 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire [14:0] \$176 ;
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire \$179 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
+  wire [14:0] \$180 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$189 ;
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$193 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$197 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$198 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$201 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$205 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$206 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire \$209 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$210 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$214 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$218 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *)
-  wire [14:0] \$222 ;
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-  wire [2:0] \$227 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *)
-  wire [2:0] \$228 ;
+  wire [2:0] \$214 ;
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-  wire \$230 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
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-  wire \$233 ;
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-  wire [2:0] \$235 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$237 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$239 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$241 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$243 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *)
-  wire \$245 ;
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-  wire [2:0] \$247 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
-  wire \$249 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
-  wire \$251 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
-  wire [5:0] \$254 ;
+  wire [5:0] \$240 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
-  wire [2:0] \$256 ;
+  wire [2:0] \$242 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
-  wire [4:0] \$258 ;
+  wire [4:0] \$244 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
-  wire [2:0] \$260 ;
+  wire [2:0] \$246 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$261 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire [2:0] \$263 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$265 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$267 ;
+  wire \$253 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$269 ;
+  wire \$255 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$271 ;
+  wire \$257 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
-  wire [5:0] \$274 ;
+  wire [5:0] \$260 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$275 ;
+  wire \$261 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire [2:0] \$277 ;
+  wire [2:0] \$263 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$279 ;
+  wire \$265 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$281 ;
+  wire \$267 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$283 ;
+  wire \$269 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$285 ;
+  wire \$271 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *)
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+  wire \$273 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
-  wire [2:0] \$289 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
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+  wire \$277 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
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+  wire \$285 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
+  wire \$287 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
+  wire [2:0] \$290 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
+  wire \$291 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
+  wire [2:0] \$293 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
+  wire \$295 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
+  wire \$297 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
+  wire \$299 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
   wire \$301 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
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@@ -40125,7 +40127,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
   wire \$315 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
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+  wire [4:0] \$318 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
   wire \$319 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
@@ -40138,672 +40140,670 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   wire \$327 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
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-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
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-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
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-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$337 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$339 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$341 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$343 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *)
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+  wire \$331 ;
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   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
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+  wire \$335 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
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+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
+  wire \$346 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
+  wire \$348 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
+  wire \$350 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire [6:0] \$352 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$354 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$356 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$358 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$362 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$364 ;
+  wire \$362 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
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+  wire [6:0] \$364 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$368 ;
+  wire \$366 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$368 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$370 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$374 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$376 ;
+  wire \$374 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$378 ;
+  wire [6:0] \$376 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$380 ;
+  wire \$378 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$380 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$382 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$386 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$388 ;
+  wire \$386 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
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+  wire [6:0] \$388 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$392 ;
+  wire \$390 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$392 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$398 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$400 ;
+  wire \$398 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$402 ;
+  wire [6:0] \$400 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$404 ;
+  wire \$402 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$404 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$410 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$412 ;
+  wire \$410 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$414 ;
+  wire [6:0] \$412 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$416 ;
+  wire \$414 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$416 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$418 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$422 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$424 ;
+  wire \$422 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$426 ;
+  wire [6:0] \$424 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$428 ;
+  wire \$426 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$428 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$434 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$436 ;
+  wire \$434 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$438 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$440 ;
+  wire \$438 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$440 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$446 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$448 ;
+  wire \$446 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$450 ;
+  wire [6:0] \$448 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$452 ;
+  wire \$450 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$452 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$458 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$460 ;
+  wire \$458 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$462 ;
+  wire [6:0] \$460 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$464 ;
+  wire \$462 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$464 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$470 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$472 ;
+  wire \$470 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$474 ;
+  wire [6:0] \$472 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$476 ;
+  wire \$474 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$476 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$478 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$482 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$484 ;
+  wire \$482 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$486 ;
+  wire [6:0] \$484 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$488 ;
+  wire \$486 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$488 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$494 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$496 ;
+  wire \$494 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$498 ;
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$500 ;
+  wire \$498 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$500 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$506 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$508 ;
+  wire \$506 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$510 ;
+  wire [6:0] \$508 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$512 ;
+  wire \$510 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$512 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
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-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$518 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$520 ;
+  wire \$518 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$522 ;
+  wire [6:0] \$520 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$524 ;
+  wire \$522 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$524 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$526 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$528 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$530 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$532 ;
+  wire \$530 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$534 ;
+  wire [6:0] \$532 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$536 ;
+  wire \$534 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$536 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$538 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$540 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$542 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$544 ;
+  wire \$542 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$546 ;
+  wire [6:0] \$544 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$548 ;
+  wire \$546 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$548 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$550 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$552 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$554 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$556 ;
+  wire \$554 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$558 ;
+  wire [6:0] \$556 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$560 ;
+  wire \$558 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$560 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$562 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$564 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$566 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$568 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$570 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$572 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$574 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$576 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$578 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$580 ;
+  wire \$566 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [6:0] \$582 ;
+  wire [6:0] \$568 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$584 ;
+  wire [6:0] \$570 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$585 ;
+  wire [6:0] \$571 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$587 ;
+  wire [6:0] \$573 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$589 ;
+  wire [6:0] \$575 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$591 ;
+  wire [6:0] \$577 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$593 ;
+  wire [6:0] \$579 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$595 ;
+  wire [6:0] \$581 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$597 ;
+  wire [6:0] \$583 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$599 ;
+  wire [6:0] \$585 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$601 ;
+  wire [6:0] \$587 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$603 ;
+  wire [6:0] \$589 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$605 ;
+  wire [6:0] \$591 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$607 ;
+  wire [6:0] \$593 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$609 ;
+  wire [6:0] \$595 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [6:0] \$611 ;
+  wire [6:0] \$597 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$613 ;
+  wire [6:0] \$599 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$615 ;
+  wire [6:0] \$601 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$617 ;
+  wire [6:0] \$603 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [6:0] \$619 ;
+  wire [6:0] \$605 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *)
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+  wire \$607 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$623 ;
+  wire \$609 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
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+  wire [2:0] \$611 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
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+  wire \$613 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *)
-  wire \$629 ;
+  wire \$615 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
-  wire \$631 ;
+  wire \$617 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *)
+  wire \$619 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$621 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  wire \$623 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
+  wire \$625 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
+  wire \$627 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
+  wire \$629 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire \$631 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$633 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$635 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$637 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$639 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$641 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$643 ;
+  wire \$641 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire \$643 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$645 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$647 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$649 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$651 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$653 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$655 ;
+  wire \$653 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire \$655 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$657 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$659 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$661 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$663 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$665 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$667 ;
+  wire \$665 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire \$667 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$669 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$671 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$673 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$675 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$677 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$679 ;
+  wire \$677 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
+  wire \$679 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$681 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
   wire \$683 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$685 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
   wire \$687 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$689 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$691 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire \$693 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$695 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$697 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$699 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$701 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$703 ;
+  wire \$689 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire \$705 ;
+  wire \$691 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [2:0] \$707 ;
+  wire [2:0] \$693 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$708 ;
+  wire \$694 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$710 ;
+  wire \$696 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire \$712 ;
+  wire \$698 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$714 ;
+  wire \$700 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire \$716 ;
+  wire \$702 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *)
-  wire \$719 ;
+  wire \$705 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
-  wire [2:0] \$721 ;
+  wire [2:0] \$707 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
-  wire \$723 ;
+  wire \$709 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *)
-  wire \$725 ;
+  wire \$711 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$727 ;
+  wire \$713 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$729 ;
+  wire \$715 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$731 ;
+  wire \$717 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$733 ;
+  wire \$719 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$735 ;
+  wire \$721 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [1:0] \$737 ;
+  wire [1:0] \$723 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$739 ;
+  wire \$725 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$741 ;
+  wire \$727 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$743 ;
+  wire \$729 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$745 ;
+  wire \$731 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$747 ;
+  wire \$733 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [1:0] \$749 ;
+  wire [1:0] \$735 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$751 ;
+  wire \$737 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$753 ;
+  wire \$739 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$755 ;
+  wire \$741 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$757 ;
+  wire \$743 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$759 ;
+  wire \$745 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [1:0] \$761 ;
+  wire [1:0] \$747 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [2:0] \$763 ;
+  wire [2:0] \$749 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [1:0] \$764 ;
+  wire [1:0] \$750 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [1:0] \$766 ;
+  wire [1:0] \$752 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *)
-  wire \$769 ;
+  wire \$755 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
-  wire [2:0] \$771 ;
+  wire [2:0] \$757 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
-  wire \$773 ;
+  wire \$759 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *)
-  wire \$775 ;
+  wire \$761 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$777 ;
+  wire \$763 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$779 ;
+  wire \$765 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$781 ;
+  wire \$767 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$783 ;
+  wire \$769 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$785 ;
+  wire \$771 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$787 ;
+  wire [2:0] \$773 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$789 ;
+  wire \$775 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$791 ;
+  wire \$777 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$793 ;
+  wire \$779 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$795 ;
+  wire \$781 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$797 ;
+  wire \$783 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [7:0] \$799 ;
+  wire [7:0] \$785 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$801 ;
+  wire \$787 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$803 ;
+  wire \$789 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$805 ;
+  wire \$791 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$807 ;
+  wire \$793 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$809 ;
+  wire \$795 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *)
-  wire [7:0] \$811 ;
+  wire [7:0] \$797 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *)
-  wire [255:0] \$813 ;
+  wire [255:0] \$799 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [255:0] \$815 ;
+  wire [255:0] \$801 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$817 ;
+  wire \$803 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$819 ;
+  wire \$805 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$821 ;
+  wire \$807 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$823 ;
+  wire \$809 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$825 ;
+  wire \$811 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *)
-  wire [7:0] \$827 ;
+  wire [7:0] \$813 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *)
-  wire [255:0] \$829 ;
+  wire [255:0] \$815 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [255:0] \$831 ;
+  wire [255:0] \$817 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [255:0] \$833 ;
+  wire [255:0] \$819 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [255:0] \$834 ;
+  wire [255:0] \$820 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$836 ;
+  wire \$822 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$838 ;
+  wire \$824 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$840 ;
+  wire \$826 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$842 ;
+  wire \$828 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$844 ;
+  wire \$830 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *)
-  wire [7:0] \$846 ;
+  wire [7:0] \$832 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *)
-  wire [255:0] \$848 ;
+  wire [255:0] \$834 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [255:0] \$850 ;
+  wire [255:0] \$836 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$852 ;
+  wire \$838 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$854 ;
+  wire \$840 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$856 ;
+  wire \$842 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$858 ;
+  wire \$844 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$860 ;
+  wire \$846 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *)
-  wire [7:0] \$862 ;
+  wire [7:0] \$848 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *)
-  wire [255:0] \$864 ;
+  wire [255:0] \$850 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [255:0] \$866 ;
+  wire [255:0] \$852 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$868 ;
+  wire \$854 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$870 ;
+  wire \$856 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$872 ;
+  wire \$858 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$874 ;
+  wire \$860 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$876 ;
+  wire \$862 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$878 ;
+  wire [2:0] \$864 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$880 ;
+  wire \$866 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$882 ;
+  wire \$868 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$884 ;
+  wire \$870 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$886 ;
+  wire \$872 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$888 ;
+  wire \$874 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$890 ;
+  wire [2:0] \$876 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$892 ;
+  wire \$878 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$894 ;
+  wire \$880 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$896 ;
+  wire \$882 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$898 ;
+  wire \$884 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$900 ;
+  wire \$886 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$902 ;
+  wire [2:0] \$888 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$904 ;
+  wire \$890 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$906 ;
+  wire \$892 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$908 ;
+  wire \$894 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$910 ;
+  wire \$896 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$912 ;
+  wire \$898 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$914 ;
+  wire [2:0] \$900 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$916 ;
+  wire \$902 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$918 ;
+  wire \$904 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$920 ;
+  wire \$906 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$922 ;
+  wire \$908 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$924 ;
+  wire \$910 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$926 ;
+  wire [2:0] \$912 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$928 ;
+  wire \$914 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$930 ;
+  wire \$916 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$932 ;
+  wire \$918 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$934 ;
+  wire \$920 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$936 ;
+  wire \$922 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [2:0] \$938 ;
+  wire [2:0] \$924 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [3:0] \$940 ;
+  wire [3:0] \$926 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [2:0] \$941 ;
+  wire [2:0] \$927 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [2:0] \$943 ;
+  wire [2:0] \$929 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
-  wire [2:0] \$945 ;
+  wire [2:0] \$931 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [2:0] \$947 ;
+  wire [2:0] \$933 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
-  wire [2:0] \$949 ;
+  wire [2:0] \$935 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *)
-  wire \$952 ;
+  wire \$938 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$954 ;
+  wire \$940 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *)
-  wire \$956 ;
+  wire \$942 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$958 ;
+  wire \$944 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
-  wire \$960 ;
+  wire \$946 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *)
-  wire \$962 ;
+  wire \$948 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *)
-  wire [9:0] \$964 ;
+  wire [9:0] \$950 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *)
-  wire \$966 ;
+  wire \$952 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
-  wire \$968 ;
+  wire \$954 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$970 ;
+  wire \$956 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$972 ;
+  wire \$958 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$974 ;
+  wire \$960 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$976 ;
+  wire \$962 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$978 ;
+  wire \$964 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$980 ;
+  wire \$966 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$982 ;
+  wire \$968 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$984 ;
+  wire \$970 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$986 ;
+  wire \$972 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *)
-  wire \$988 ;
+  wire \$974 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
+  wire \$976 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
+  wire \$978 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
+  wire \$980 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
+  wire \$986 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *)
+  wire [6:0] \$988 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *)
   wire \$990 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *)
+  wire \$993 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$992 ;
+  wire \$997 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$994 ;
+  wire \$999 ;
   (* enum_base_type = "SVPtype" *)
   (* enum_value_00 = "NONE" *)
   (* enum_value_01 = "P1" *)
@@ -40951,81 +40951,81 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
   wire [6:0] addr_en;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1020 ;
+  wire [6:0] \addr_en$1006 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1043 ;
+  wire [6:0] \addr_en$1029 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1061 ;
+  wire [6:0] \addr_en$1047 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1083 ;
+  wire [6:0] \addr_en$1069 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1103 ;
+  wire [6:0] \addr_en$1089 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1123 ;
+  wire [6:0] \addr_en$1109 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1142 ;
+  wire [6:0] \addr_en$1128 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1160 ;
+  wire [6:0] \addr_en$1146 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [6:0] \addr_en$1176 ;
+  wire [6:0] \addr_en$1162 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [7:0] \addr_en$1250 ;
+  wire [7:0] \addr_en$1236 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1278 ;
+  wire [255:0] \addr_en$1264 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1298 ;
+  wire [255:0] \addr_en$1284 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1318 ;
+  wire [255:0] \addr_en$1304 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1338 ;
+  wire [255:0] \addr_en$1324 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1358 ;
+  wire [255:0] \addr_en$1344 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [255:0] \addr_en$1378 ;
+  wire [255:0] \addr_en$1364 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [1:0] \addr_en$1425 ;
+  wire [1:0] \addr_en$1411 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [1:0] \addr_en$1441 ;
+  wire [1:0] \addr_en$1427 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [1:0] \addr_en$1457 ;
+  wire [1:0] \addr_en$1443 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1491 ;
+  wire [2:0] \addr_en$1477 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1507 ;
+  wire [2:0] \addr_en$1493 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1523 ;
+  wire [2:0] \addr_en$1509 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1539 ;
+  wire [2:0] \addr_en$1525 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1575 ;
+  wire \addr_en$1561 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1591 ;
+  wire \addr_en$1577 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1607 ;
+  wire \addr_en$1593 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1623 ;
+  wire \addr_en$1609 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1670 ;
+  wire [2:0] \addr_en$1656 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1686 ;
+  wire [2:0] \addr_en$1672 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1702 ;
+  wire [2:0] \addr_en$1688 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1718 ;
+  wire [2:0] \addr_en$1704 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1734 ;
+  wire [2:0] \addr_en$1720 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1750 ;
+  wire [2:0] \addr_en$1736 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1802 ;
+  wire \addr_en$1788 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire \addr_en$1818 ;
+  wire \addr_en$1804 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [1:0] \addr_en$1842 ;
+  wire [1:0] \addr_en$1828 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [2:0] \addr_en$1862 ;
+  wire [2:0] \addr_en$1848 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *)
-  wire [9:0] \addr_en$1882 ;
+  wire [9:0] \addr_en$1868 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *)
   wire [255:0] addr_en_CR_cr_a_branch0_1;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *)
@@ -41139,21 +41139,21 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   input [7:0] core_core_cr_wr;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal ;
+  input core_core_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$3 ;
+  input core_core_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$4 ;
+  input core_core_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$5 ;
+  input core_core_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$6 ;
+  input core_core_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$7 ;
+  input core_core_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$8 ;
+  input core_core_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \core_core_exc_$signal$9 ;
+  input core_core_exc_segment_fault;
   (* enum_base_type = "Function" *)
   (* enum_value_000000000000000 = "NONE" *)
   (* enum_value_000000000000010 = "ALU" *)
@@ -41412,7 +41412,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   input [63:0] data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  input [63:0] \data_i$11 ;
+  input [63:0] \data_i$4 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
   input dbus__ack;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
@@ -42756,7 +42756,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *)
   wire en_trap0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_o_$signal ;
+  output exc_o_happened;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [3:0] fast_dest1__addr;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -42782,227 +42782,227 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_cr_a_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_cr_a_ok$123 ;
+  wire \fus_cr_a_ok$116 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_cr_a_ok$124 ;
+  wire \fus_cr_a_ok$117 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_cr_a_ok$125 ;
+  wire \fus_cr_a_ok$118 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_cr_a_ok$126 ;
+  wire \fus_cr_a_ok$119 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_cr_a_ok$127 ;
+  wire \fus_cr_a_ok$120 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
   wire fus_cu_busy_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$14 ;
+  wire \fus_cu_busy_o$10 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$17 ;
+  wire \fus_cu_busy_o$13 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$20 ;
+  wire \fus_cu_busy_o$16 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$23 ;
+  wire \fus_cu_busy_o$19 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$26 ;
+  wire \fus_cu_busy_o$22 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$29 ;
+  wire \fus_cu_busy_o$25 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$32 ;
+  wire \fus_cu_busy_o$28 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$35 ;
+  wire \fus_cu_busy_o$31 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
-  wire \fus_cu_busy_o$38 ;
+  wire \fus_cu_busy_o$7 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
   reg fus_cu_issue_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$13 ;
+  reg \fus_cu_issue_i$12 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$16 ;
+  reg \fus_cu_issue_i$15 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$19 ;
+  reg \fus_cu_issue_i$18 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$22 ;
+  reg \fus_cu_issue_i$21 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$25 ;
+  reg \fus_cu_issue_i$24 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$28 ;
+  reg \fus_cu_issue_i$27 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$31 ;
+  reg \fus_cu_issue_i$30 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$34 ;
+  reg \fus_cu_issue_i$6 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
-  reg \fus_cu_issue_i$37 ;
+  reg \fus_cu_issue_i$9 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
   wire [3:0] fus_cu_rd__go_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_rd__go_i$41 ;
+  wire [5:0] \fus_cu_rd__go_i$34 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [4:0] \fus_cu_rd__go_i$44 ;
+  wire [4:0] \fus_cu_rd__go_i$37 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__go_i$47 ;
+  wire [2:0] \fus_cu_rd__go_i$40 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__go_i$50 ;
+  wire [2:0] \fus_cu_rd__go_i$43 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__go_i$53 ;
+  wire [2:0] \fus_cu_rd__go_i$46 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [4:0] \fus_cu_rd__go_i$56 ;
+  wire [4:0] \fus_cu_rd__go_i$49 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__go_i$59 ;
+  wire [2:0] \fus_cu_rd__go_i$52 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_rd__go_i$66 ;
+  wire [5:0] \fus_cu_rd__go_i$59 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__go_i$82 ;
+  wire [2:0] \fus_cu_rd__go_i$75 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
   wire [3:0] fus_cu_rd__rel_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_rd__rel_o$40 ;
+  wire [5:0] \fus_cu_rd__rel_o$33 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [4:0] \fus_cu_rd__rel_o$43 ;
+  wire [4:0] \fus_cu_rd__rel_o$36 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__rel_o$46 ;
+  wire [2:0] \fus_cu_rd__rel_o$39 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__rel_o$49 ;
+  wire [2:0] \fus_cu_rd__rel_o$42 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__rel_o$52 ;
+  wire [2:0] \fus_cu_rd__rel_o$45 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [4:0] \fus_cu_rd__rel_o$55 ;
+  wire [4:0] \fus_cu_rd__rel_o$48 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__rel_o$58 ;
+  wire [2:0] \fus_cu_rd__rel_o$51 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_rd__rel_o$65 ;
+  wire [5:0] \fus_cu_rd__rel_o$58 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_rd__rel_o$81 ;
+  wire [2:0] \fus_cu_rd__rel_o$74 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
   reg [3:0] fus_cu_rdmaskn_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [5:0] \fus_cu_rdmaskn_i$15 ;
+  reg [2:0] \fus_cu_rdmaskn_i$11 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [2:0] \fus_cu_rdmaskn_i$18 ;
+  reg [4:0] \fus_cu_rdmaskn_i$14 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [4:0] \fus_cu_rdmaskn_i$21 ;
+  reg [2:0] \fus_cu_rdmaskn_i$17 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [2:0] \fus_cu_rdmaskn_i$24 ;
+  reg [5:0] \fus_cu_rdmaskn_i$20 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [5:0] \fus_cu_rdmaskn_i$27 ;
+  reg [2:0] \fus_cu_rdmaskn_i$23 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [2:0] \fus_cu_rdmaskn_i$30 ;
+  reg [2:0] \fus_cu_rdmaskn_i$26 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [2:0] \fus_cu_rdmaskn_i$33 ;
+  reg [4:0] \fus_cu_rdmaskn_i$29 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [4:0] \fus_cu_rdmaskn_i$36 ;
+  reg [2:0] \fus_cu_rdmaskn_i$32 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
-  reg [2:0] \fus_cu_rdmaskn_i$39 ;
+  reg [5:0] \fus_cu_rdmaskn_i$8 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
   wire [4:0] fus_cu_wr__go_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [1:0] \fus_cu_wr__go_i$101 ;
+  wire [3:0] \fus_cu_wr__go_i$100 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_wr__go_i$104 ;
+  wire [3:0] \fus_cu_wr__go_i$103 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [3:0] \fus_cu_wr__go_i$107 ;
+  wire [2:0] \fus_cu_wr__go_i$106 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [3:0] \fus_cu_wr__go_i$110 ;
+  wire [1:0] \fus_cu_wr__go_i$108 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__go_i$113 ;
+  wire [2:0] \fus_cu_wr__go_i$143 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [1:0] \fus_cu_wr__go_i$115 ;
+  wire [2:0] \fus_cu_wr__go_i$88 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__go_i$150 ;
+  wire [6:0] \fus_cu_wr__go_i$91 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__go_i$95 ;
+  wire [1:0] \fus_cu_wr__go_i$94 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [6:0] \fus_cu_wr__go_i$98 ;
+  wire [5:0] \fus_cu_wr__go_i$97 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
   wire [4:0] fus_cu_wr__rel_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [1:0] \fus_cu_wr__rel_o$100 ;
+  wire [3:0] \fus_cu_wr__rel_o$102 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [5:0] \fus_cu_wr__rel_o$103 ;
+  wire [2:0] \fus_cu_wr__rel_o$105 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [3:0] \fus_cu_wr__rel_o$106 ;
+  wire [1:0] \fus_cu_wr__rel_o$107 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [3:0] \fus_cu_wr__rel_o$109 ;
+  wire [2:0] \fus_cu_wr__rel_o$142 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__rel_o$112 ;
+  wire [2:0] \fus_cu_wr__rel_o$87 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [1:0] \fus_cu_wr__rel_o$114 ;
+  wire [6:0] \fus_cu_wr__rel_o$90 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__rel_o$149 ;
+  wire [1:0] \fus_cu_wr__rel_o$93 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [2:0] \fus_cu_wr__rel_o$94 ;
+  wire [5:0] \fus_cu_wr__rel_o$96 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
-  wire [6:0] \fus_cu_wr__rel_o$97 ;
+  wire [3:0] \fus_cu_wr__rel_o$99 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [63:0] fus_dest1_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$116 ;
+  wire [63:0] \fus_dest1_o$109 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$117 ;
+  wire [63:0] \fus_dest1_o$110 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$118 ;
+  wire [63:0] \fus_dest1_o$111 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$119 ;
+  wire [63:0] \fus_dest1_o$112 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$120 ;
+  wire [63:0] \fus_dest1_o$113 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$121 ;
+  wire [63:0] \fus_dest1_o$114 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$122 ;
+  wire [63:0] \fus_dest1_o$115 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest1_o$154 ;
+  wire [63:0] \fus_dest1_o$147 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [31:0] fus_dest2_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [3:0] \fus_dest2_o$128 ;
+  wire [3:0] \fus_dest2_o$121 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [3:0] \fus_dest2_o$129 ;
+  wire [3:0] \fus_dest2_o$122 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [3:0] \fus_dest2_o$130 ;
+  wire [3:0] \fus_dest2_o$123 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [3:0] \fus_dest2_o$131 ;
+  wire [3:0] \fus_dest2_o$124 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [3:0] \fus_dest2_o$132 ;
+  wire [3:0] \fus_dest2_o$125 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest2_o$155 ;
+  wire [63:0] \fus_dest2_o$148 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest2_o$157 ;
+  wire [63:0] \fus_dest2_o$150 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest2_o$164 ;
+  wire [63:0] \fus_dest2_o$157 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [3:0] fus_dest3_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [1:0] \fus_dest3_o$135 ;
+  wire [1:0] \fus_dest3_o$128 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [1:0] \fus_dest3_o$136 ;
+  wire [1:0] \fus_dest3_o$129 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [1:0] \fus_dest3_o$140 ;
+  wire [1:0] \fus_dest3_o$133 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [1:0] \fus_dest3_o$141 ;
+  wire [1:0] \fus_dest3_o$134 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest3_o$156 ;
+  wire [63:0] \fus_dest3_o$149 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest3_o$158 ;
+  wire [63:0] \fus_dest3_o$151 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest3_o$161 ;
+  wire [63:0] \fus_dest3_o$154 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [1:0] fus_dest4_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire \fus_dest4_o$146 ;
+  wire \fus_dest4_o$139 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire \fus_dest4_o$147 ;
+  wire \fus_dest4_o$140 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire \fus_dest4_o$148 ;
+  wire \fus_dest4_o$141 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest4_o$159 ;
+  wire [63:0] \fus_dest4_o$152 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [1:0] fus_dest5_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire \fus_dest5_o$145 ;
+  wire \fus_dest5_o$138 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest5_o$162 ;
+  wire [63:0] \fus_dest5_o$155 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [1:0] fus_dest6_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
-  wire [63:0] \fus_dest6_o$163 ;
+  wire [63:0] \fus_dest6_o$156 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
   wire [31:0] fus_dest7_o;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -43010,13 +43010,13 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_fast1_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_fast1_ok$151 ;
+  wire \fus_fast1_ok$144 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_fast1_ok$152 ;
+  wire \fus_fast1_ok$145 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_fast2_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_fast2_ok$153 ;
+  wire \fus_fast2_ok$146 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_fast3_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -43032,21 +43032,21 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   wire [3:0] fus_ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal ;
+  wire fus_ldst_port0_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$165 ;
+  wire fus_ldst_port0_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$166 ;
+  wire fus_ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$167 ;
+  wire fus_ldst_port0_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$168 ;
+  wire fus_ldst_port0_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$169 ;
+  wire fus_ldst_port0_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$170 ;
+  wire fus_ldst_port0_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \fus_ldst_port0_exc_$signal$171 ;
+  wire fus_ldst_port0_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   wire fus_ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -43066,25 +43066,25 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_nia_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_nia_ok$160 ;
+  wire \fus_nia_ok$153 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [63:0] fus_o;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_o_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$102 ;
+  wire \fus_o_ok$101 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$105 ;
+  wire \fus_o_ok$104 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$108 ;
+  wire \fus_o_ok$86 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$111 ;
+  wire \fus_o_ok$89 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$93 ;
+  wire \fus_o_ok$92 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$96 ;
+  wire \fus_o_ok$95 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_o_ok$99 ;
+  wire \fus_o_ok$98 ;
   (* enum_base_type = "SVPtype" *)
   (* enum_value_00 = "NONE" *)
   (* enum_value_01 = "P1" *)
@@ -44451,109 +44451,109 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg [63:0] fus_src1_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$62 ;
+  reg [63:0] \fus_src1_i$55 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$63 ;
+  reg [63:0] \fus_src1_i$56 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$64 ;
+  reg [63:0] \fus_src1_i$57 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$67 ;
+  reg [63:0] \fus_src1_i$60 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$68 ;
+  reg [63:0] \fus_src1_i$61 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$69 ;
+  reg [63:0] \fus_src1_i$62 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$70 ;
+  reg [63:0] \fus_src1_i$63 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$71 ;
+  reg [63:0] \fus_src1_i$64 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src1_i$86 ;
+  reg [63:0] \fus_src1_i$79 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg [63:0] fus_src2_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$42 ;
+  reg [63:0] \fus_src2_i$35 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$45 ;
+  reg [63:0] \fus_src2_i$38 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$48 ;
+  reg [63:0] \fus_src2_i$41 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$51 ;
+  reg [63:0] \fus_src2_i$44 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$54 ;
+  reg [63:0] \fus_src2_i$47 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$57 ;
+  reg [63:0] \fus_src2_i$50 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$60 ;
+  reg [63:0] \fus_src2_i$53 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$89 ;
+  reg [63:0] \fus_src2_i$82 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src2_i$92 ;
+  reg [63:0] \fus_src2_i$85 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg [63:0] fus_src3_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src3_i$61 ;
+  reg [63:0] \fus_src3_i$54 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg \fus_src3_i$72 ;
+  reg \fus_src3_i$65 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg \fus_src3_i$73 ;
+  reg \fus_src3_i$66 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg \fus_src3_i$74 ;
+  reg \fus_src3_i$67 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg \fus_src3_i$75 ;
+  reg \fus_src3_i$68 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [31:0] \fus_src3_i$79 ;
+  reg [31:0] \fus_src3_i$72 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [3:0] \fus_src3_i$83 ;
+  reg [3:0] \fus_src3_i$76 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src3_i$87 ;
+  reg [63:0] \fus_src3_i$80 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src3_i$88 ;
+  reg [63:0] \fus_src3_i$81 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg fus_src4_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg \fus_src4_i$76 ;
+  reg \fus_src4_i$69 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [1:0] \fus_src4_i$77 ;
+  reg [1:0] \fus_src4_i$70 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [3:0] \fus_src4_i$80 ;
+  reg [3:0] \fus_src4_i$73 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src4_i$90 ;
+  reg [63:0] \fus_src4_i$83 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg [1:0] fus_src5_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [1:0] \fus_src5_i$78 ;
+  reg [1:0] \fus_src5_i$71 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [3:0] \fus_src5_i$84 ;
+  reg [3:0] \fus_src5_i$77 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [63:0] \fus_src5_i$91 ;
+  reg [63:0] \fus_src5_i$84 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
   reg [1:0] fus_src6_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
-  reg [3:0] \fus_src6_i$85 ;
+  reg [3:0] \fus_src6_i$78 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_svstate_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_xer_ca_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_ca_ok$133 ;
+  wire \fus_xer_ca_ok$126 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_ca_ok$134 ;
+  wire \fus_xer_ca_ok$127 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_xer_ov_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_ov_ok$137 ;
+  wire \fus_xer_ov_ok$130 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_ov_ok$138 ;
+  wire \fus_xer_ov_ok$131 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_ov_ok$139 ;
+  wire \fus_xer_ov_ok$132 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire fus_xer_so_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_so_ok$142 ;
+  wire \fus_xer_so_ok$135 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_so_ok$143 ;
+  wire \fus_xer_so_ok$136 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \fus_xer_so_ok$144 ;
+  wire \fus_xer_so_ok$137 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [4:0] int_dest1__addr;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -44569,7 +44569,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   input [3:0] issue__addr;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  input [3:0] \issue__addr$12 ;
+  input [3:0] \issue__addr$5 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   input [63:0] issue__data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -44845,7 +44845,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [3:0] spr_spr1__addr;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [3:0] \spr_spr1__addr$179 ;
+  wire [3:0] \spr_spr1__addr$165 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [63:0] spr_spr1__data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -44857,15 +44857,15 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [63:0] state_data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [63:0] \state_data_i$176 ;
+  wire [63:0] \state_data_i$162 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [63:0] \state_data_i$177 ;
+  wire [63:0] \state_data_i$163 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   output [2:0] state_nia_wen;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [2:0] state_wen;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [2:0] \state_wen$178 ;
+  wire [2:0] \state_wen$164 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   output [63:0] sv__data_o;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -44873,411 +44873,411 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *)
   wire sv_a_nz;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
-  wire \sv_a_nz$180 ;
+  wire \sv_a_nz$166 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
-  wire \sv_a_nz$181 ;
+  wire \sv_a_nz$167 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
-  wire \sv_a_nz$182 ;
+  wire \sv_a_nz$168 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
-  wire \sv_a_nz$183 ;
+  wire \sv_a_nz$169 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
-  wire \sv_a_nz$184 ;
+  wire \sv_a_nz$170 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
   input wb_dcache_en;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   input [2:0] wen;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  input [2:0] \wen$10 ;
+  input [2:0] \wen$3 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
   wire wp;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1017 ;
+  wire \wp$1003 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1040 ;
+  wire \wp$1026 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1058 ;
+  wire \wp$1044 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1080 ;
+  wire \wp$1066 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1100 ;
+  wire \wp$1086 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1120 ;
+  wire \wp$1106 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1139 ;
+  wire \wp$1125 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1157 ;
+  wire \wp$1143 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1173 ;
+  wire \wp$1159 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1247 ;
+  wire \wp$1233 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1275 ;
+  wire \wp$1261 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1295 ;
+  wire \wp$1281 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1315 ;
+  wire \wp$1301 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1335 ;
+  wire \wp$1321 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1355 ;
+  wire \wp$1341 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1375 ;
+  wire \wp$1361 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1422 ;
+  wire \wp$1408 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1438 ;
+  wire \wp$1424 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1454 ;
+  wire \wp$1440 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1488 ;
+  wire \wp$1474 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1504 ;
+  wire \wp$1490 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1520 ;
+  wire \wp$1506 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1536 ;
+  wire \wp$1522 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1572 ;
+  wire \wp$1558 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1588 ;
+  wire \wp$1574 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1604 ;
+  wire \wp$1590 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1620 ;
+  wire \wp$1606 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1667 ;
+  wire \wp$1653 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1683 ;
+  wire \wp$1669 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1699 ;
+  wire \wp$1685 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1715 ;
+  wire \wp$1701 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1731 ;
+  wire \wp$1717 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1747 ;
+  wire \wp$1733 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1799 ;
+  wire \wp$1785 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1815 ;
+  wire \wp$1801 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1839 ;
+  wire \wp$1825 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1859 ;
+  wire \wp$1845 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *)
-  wire \wp$1879 ;
+  wire \wp$1865 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
   wire wr_pick;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1006 ;
+  wire \wr_pick$1011 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1025 ;
+  wire \wr_pick$1034 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1048 ;
+  wire \wr_pick$1052 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1066 ;
+  wire \wr_pick$1074 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1088 ;
+  wire \wr_pick$1094 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1108 ;
+  wire \wr_pick$1114 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1128 ;
+  wire \wr_pick$1133 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1147 ;
+  wire \wr_pick$1151 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1165 ;
+  wire \wr_pick$1225 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1239 ;
+  wire \wr_pick$1253 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1267 ;
+  wire \wr_pick$1273 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1287 ;
+  wire \wr_pick$1293 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1307 ;
+  wire \wr_pick$1313 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1327 ;
+  wire \wr_pick$1333 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1347 ;
+  wire \wr_pick$1353 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1367 ;
+  wire \wr_pick$1400 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1414 ;
+  wire \wr_pick$1416 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1430 ;
+  wire \wr_pick$1432 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1446 ;
+  wire \wr_pick$1466 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1480 ;
+  wire \wr_pick$1482 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1496 ;
+  wire \wr_pick$1498 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1512 ;
+  wire \wr_pick$1514 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1528 ;
+  wire \wr_pick$1550 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1564 ;
+  wire \wr_pick$1566 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1580 ;
+  wire \wr_pick$1582 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1596 ;
+  wire \wr_pick$1598 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1612 ;
+  wire \wr_pick$1642 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1656 ;
+  wire \wr_pick$1661 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1675 ;
+  wire \wr_pick$1677 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1691 ;
+  wire \wr_pick$1693 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1707 ;
+  wire \wr_pick$1709 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1723 ;
+  wire \wr_pick$1725 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1739 ;
+  wire \wr_pick$1777 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1791 ;
+  wire \wr_pick$1793 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1807 ;
+  wire \wr_pick$1817 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1831 ;
+  wire \wr_pick$1837 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1851 ;
+  wire \wr_pick$1857 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *)
-  wire \wr_pick$1871 ;
+  wire \wr_pick$992 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
   reg wr_pick_dly = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1009  = 1'h0;
+  reg \wr_pick_dly$1014  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1009$next ;
+  reg \wr_pick_dly$1014$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1028  = 1'h0;
+  reg \wr_pick_dly$1037  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1028$next ;
+  reg \wr_pick_dly$1037$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1051  = 1'h0;
+  reg \wr_pick_dly$1055  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1051$next ;
+  reg \wr_pick_dly$1055$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1069  = 1'h0;
+  reg \wr_pick_dly$1077  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1069$next ;
+  reg \wr_pick_dly$1077$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1091  = 1'h0;
+  reg \wr_pick_dly$1097  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1091$next ;
+  reg \wr_pick_dly$1097$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1111  = 1'h0;
+  reg \wr_pick_dly$1117  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1111$next ;
+  reg \wr_pick_dly$1117$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1131  = 1'h0;
+  reg \wr_pick_dly$1136  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1131$next ;
+  reg \wr_pick_dly$1136$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1150  = 1'h0;
+  reg \wr_pick_dly$1154  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1150$next ;
+  reg \wr_pick_dly$1154$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1168  = 1'h0;
+  reg \wr_pick_dly$1228  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1168$next ;
+  reg \wr_pick_dly$1228$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1242  = 1'h0;
+  reg \wr_pick_dly$1256  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1242$next ;
+  reg \wr_pick_dly$1256$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1270  = 1'h0;
+  reg \wr_pick_dly$1276  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1270$next ;
+  reg \wr_pick_dly$1276$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1290  = 1'h0;
+  reg \wr_pick_dly$1296  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1290$next ;
+  reg \wr_pick_dly$1296$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1310  = 1'h0;
+  reg \wr_pick_dly$1316  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1310$next ;
+  reg \wr_pick_dly$1316$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1330  = 1'h0;
+  reg \wr_pick_dly$1336  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1330$next ;
+  reg \wr_pick_dly$1336$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1350  = 1'h0;
+  reg \wr_pick_dly$1356  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1350$next ;
+  reg \wr_pick_dly$1356$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1370  = 1'h0;
+  reg \wr_pick_dly$1403  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1370$next ;
+  reg \wr_pick_dly$1403$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1417  = 1'h0;
+  reg \wr_pick_dly$1419  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1417$next ;
+  reg \wr_pick_dly$1419$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1433  = 1'h0;
+  reg \wr_pick_dly$1435  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1433$next ;
+  reg \wr_pick_dly$1435$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1449  = 1'h0;
+  reg \wr_pick_dly$1469  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1449$next ;
+  reg \wr_pick_dly$1469$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1483  = 1'h0;
+  reg \wr_pick_dly$1485  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1483$next ;
+  reg \wr_pick_dly$1485$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1499  = 1'h0;
+  reg \wr_pick_dly$1501  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1499$next ;
+  reg \wr_pick_dly$1501$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1515  = 1'h0;
+  reg \wr_pick_dly$1517  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1515$next ;
+  reg \wr_pick_dly$1517$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1531  = 1'h0;
+  reg \wr_pick_dly$1553  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1531$next ;
+  reg \wr_pick_dly$1553$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1567  = 1'h0;
+  reg \wr_pick_dly$1569  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1567$next ;
+  reg \wr_pick_dly$1569$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1583  = 1'h0;
+  reg \wr_pick_dly$1585  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1583$next ;
+  reg \wr_pick_dly$1585$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1599  = 1'h0;
+  reg \wr_pick_dly$1601  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1599$next ;
+  reg \wr_pick_dly$1601$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1615  = 1'h0;
+  reg \wr_pick_dly$1645  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1615$next ;
+  reg \wr_pick_dly$1645$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1659  = 1'h0;
+  reg \wr_pick_dly$1664  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1659$next ;
+  reg \wr_pick_dly$1664$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1678  = 1'h0;
+  reg \wr_pick_dly$1680  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1678$next ;
+  reg \wr_pick_dly$1680$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1694  = 1'h0;
+  reg \wr_pick_dly$1696  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1694$next ;
+  reg \wr_pick_dly$1696$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1710  = 1'h0;
+  reg \wr_pick_dly$1712  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1710$next ;
+  reg \wr_pick_dly$1712$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1726  = 1'h0;
+  reg \wr_pick_dly$1728  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1726$next ;
+  reg \wr_pick_dly$1728$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1742  = 1'h0;
+  reg \wr_pick_dly$1780  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1742$next ;
+  reg \wr_pick_dly$1780$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1794  = 1'h0;
+  reg \wr_pick_dly$1796  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1794$next ;
+  reg \wr_pick_dly$1796$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1810  = 1'h0;
+  reg \wr_pick_dly$1820  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1810$next ;
+  reg \wr_pick_dly$1820$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1834  = 1'h0;
+  reg \wr_pick_dly$1840  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1834$next ;
+  reg \wr_pick_dly$1840$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1854  = 1'h0;
+  reg \wr_pick_dly$1860  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1854$next ;
+  reg \wr_pick_dly$1860$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1874  = 1'h0;
+  reg \wr_pick_dly$995  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
-  reg \wr_pick_dly$1874$next ;
+  reg \wr_pick_dly$995$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
   reg \wr_pick_dly$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire wr_pick_rise;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1010 ;
+  wire \wr_pick_rise$1001 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
+  wire \wr_pick_rise$1002 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1015 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1016 ;
+  wire \wr_pick_rise$1020 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1029 ;
+  wire \wr_pick_rise$1021 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1034 ;
+  wire \wr_pick_rise$1022 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1035 ;
+  wire \wr_pick_rise$1023 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1036 ;
+  wire \wr_pick_rise$1024 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1037 ;
+  wire \wr_pick_rise$1025 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1038 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1039 ;
+  wire \wr_pick_rise$1043 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1052 ;
+  wire \wr_pick_rise$1056 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1057 ;
+  wire \wr_pick_rise$1061 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1070 ;
+  wire \wr_pick_rise$1062 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1075 ;
+  wire \wr_pick_rise$1063 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1076 ;
+  wire \wr_pick_rise$1064 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1077 ;
+  wire \wr_pick_rise$1065 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1078 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1079 ;
+  wire \wr_pick_rise$1083 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1092 ;
+  wire \wr_pick_rise$1084 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1097 ;
+  wire \wr_pick_rise$1085 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1098 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1099 ;
+  wire \wr_pick_rise$1103 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1112 ;
+  wire \wr_pick_rise$1104 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1117 ;
+  wire \wr_pick_rise$1105 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1118 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1119 ;
+  wire \wr_pick_rise$1123 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1132 ;
+  wire \wr_pick_rise$1124 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
   wire \wr_pick_rise$1137 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1138 ;
+  wire \wr_pick_rise$1142 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1151 ;
+  wire \wr_pick_rise$1646 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1156 ;
+  wire \wr_pick_rise$1651 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1660 ;
+  wire \wr_pick_rise$1652 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1665 ;
+  wire \wr_pick_rise$982 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$1666 ;
+  wire \wr_pick_rise$983 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$996 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$997 ;
+  wire \wr_pick_rise$984 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$998 ;
+  wire \wr_pick_rise$985 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
-  wire \wr_pick_rise$999 ;
+  wire \wr_pick_rise$996 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *)
   wire wrflag_alu0_cr_a_1;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *)
@@ -45425,9 +45425,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [1:0] xer_data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [1:0] \xer_data_i$172 ;
+  wire [1:0] \xer_data_i$158 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [1:0] \xer_data_i$174 ;
+  wire [1:0] \xer_data_i$160 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [1:0] xer_src1__data_o;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -45443,416 +45443,418 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [2:0] xer_wen;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [2:0] \xer_wen$173 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [2:0] \xer_wen$175 ;
-  assign \$1000  = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1002  = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1004  = \fus_o_ok$93  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ;
-  assign \$1007  = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1011  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1009 ;
-  assign \$1013  = \wr_pick$1006  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1011 ;
-  assign \$1018  = \wr_pick$1006  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1021  = \wp$1017  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1023  = \fus_o_ok$96  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1026  = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1030  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1028 ;
-  assign \$1032  = \wr_pick$1025  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1030 ;
-  assign \$1041  = \wr_pick$1025  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1044  = \wp$1040  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1046  = \fus_o_ok$99  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$23 ;
-  assign \$1049  = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1053  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1051 ;
-  assign \$1055  = \wr_pick$1048  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1053 ;
-  assign \$1059  = \wr_pick$1048  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1062  = \wp$1058  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1064  = \fus_o_ok$102  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$1067  = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1071  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ;
-  assign \$1073  = \wr_pick$1066  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ;
-  assign \$1081  = \wr_pick$1066  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1084  = \wp$1080  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1086  = \fus_o_ok$105  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ;
-  assign \$1089  = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1093  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1091 ;
-  assign \$1095  = \wr_pick$1088  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1093 ;
-  assign \$1101  = \wr_pick$1088  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1104  = \wp$1100  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1106  = \fus_o_ok$108  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ;
-  assign \$1109  = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1113  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1111 ;
-  assign \$1115  = \wr_pick$1108  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1113 ;
-  assign \$1121  = \wr_pick$1108  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1124  = \wp$1120  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1126  = \fus_o_ok$111  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ;
-  assign \$1129  = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1133  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1131 ;
-  assign \$1135  = \wr_pick$1128  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1133 ;
-  assign \$1140  = \wr_pick$1128  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1143  = \wp$1139  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1145  = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$38 ;
-  assign \$1148  = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1152  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1150 ;
-  assign \$1154  = \wr_pick$1147  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1152 ;
-  assign \$1158  = \wr_pick$1147  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1161  = \wp$1157  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
-  assign \$1163  = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$38 ;
-  assign \$1166  = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$1169  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1168 ;
-  assign \$1171  = \wr_pick$1165  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1169 ;
-  assign \$1174  = \wr_pick$1165  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
-  assign \$1177  = \wp$1173  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_ea : 7'h00;
-  assign \$1180  = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$116 ;
-  assign \$1182  = \fus_dest1_o$118  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$119 ;
-  assign \$1184  = \fus_dest1_o$117  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1182 ;
-  assign \$1186  = \$1180  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1184 ;
-  assign \$1188  = \fus_dest1_o$120  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$121 ;
-  assign \$1190  = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea };
-  assign \$1192  = \fus_dest1_o$122  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1190 ;
-  assign \$1194  = \$1188  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1192 ;
-  assign \$1196  = \$1186  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1194 ;
-  assign \$1199  = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1020 ;
-  assign \$1201  = \addr_en$1061  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1083 ;
-  assign \$1203  = \addr_en$1043  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1201 ;
-  assign \$1205  = \$1199  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1203 ;
-  assign \$1207  = \addr_en$1103  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1123 ;
-  assign \$1209  = \addr_en$1160  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1176 ;
-  assign \$1211  = \addr_en$1142  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ;
-  assign \$1213  = \$1207  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1211 ;
-  assign \$1215  = \$1205  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1213 ;
-  assign \$1217  = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1017 ;
-  assign \$1219  = \wp$1058  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1080 ;
-  assign \$1221  = \wp$1040  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1219 ;
-  assign \$1223  = \$1217  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1221 ;
-  assign \$1225  = \wp$1100  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1120 ;
-  assign \$1227  = \wp$1157  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1173 ;
-  assign \$1229  = \wp$1139  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1227 ;
-  assign \$1231  = \$1225  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1229 ;
-  assign \$1233  = \$1223  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1231 ;
-  assign \$1235  = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ;
-  assign \$1237  = \fus_cu_wr__rel_o$94 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
-  assign \$1240  = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_full_cr_en_o;
-  assign \$1243  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1242 ;
-  assign \$1245  = \wr_pick$1239  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1243 ;
-  assign \$1248  = \wr_pick$1239  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_full_cr_en_o;
-  assign \$1251  = \wp$1247  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_core_cr_wr : 8'h00;
-  assign \$1253  = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
-  assign \$1255  = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
-  assign \$1257  = \fus_cu_wr__rel_o$94 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
-  assign \$1259  = \fus_cu_wr__rel_o$100 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4];
-  assign \$1261  = \fus_cu_wr__rel_o$106 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
-  assign \$1263  = \fus_cu_wr__rel_o$109 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
-  assign \$1265  = \fus_cu_wr__rel_o$112 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
-  assign \$1268  = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1271  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1270 ;
-  assign \$1273  = \wr_pick$1267  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1271 ;
-  assign \$1276  = \wr_pick$1267  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1279  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1281  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1279 ;
-  assign \$1283  = \wp$1275  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1281  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1285  = \fus_cr_a_ok$123  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ;
-  assign \$1288  = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1291  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1290 ;
-  assign \$1293  = \wr_pick$1287  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1291 ;
-  assign \$1296  = \wr_pick$1287  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1299  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1301  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1299 ;
-  assign \$1303  = \wp$1295  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1301  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1305  = \fus_cr_a_ok$124  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$23 ;
-  assign \$1308  = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1311  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1310 ;
-  assign \$1313  = \wr_pick$1307  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1311 ;
-  assign \$1316  = \wr_pick$1307  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1319  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1321  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1319 ;
-  assign \$1323  = \wp$1315  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1321  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1325  = \fus_cr_a_ok$125  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ;
-  assign \$1328  = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1331  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1330 ;
-  assign \$1333  = \wr_pick$1327  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1331 ;
-  assign \$1336  = \wr_pick$1327  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1339  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1341  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1339 ;
-  assign \$1343  = \wp$1335  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1341  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1345  = \fus_cr_a_ok$126  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ;
-  assign \$1348  = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1351  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1350 ;
-  assign \$1353  = \wr_pick$1347  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1351 ;
-  assign \$1356  = \wr_pick$1347  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1359  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1361  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1359 ;
-  assign \$1363  = \wp$1355  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1361  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1365  = \fus_cr_a_ok$127  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ;
-  assign \$1368  = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
-  assign \$1371  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1370 ;
-  assign \$1373  = \wr_pick$1367  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1371 ;
-  assign \$1376  = \wr_pick$1367  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
-  assign \$1379  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
-  assign \$1381  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1379 ;
-  assign \$1383  = \wp$1375  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1381  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$1385  = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$129 ;
-  assign \$1387  = \fus_dest2_o$128  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1385 ;
-  assign \$1389  = \fus_dest2_o$131  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$132 ;
-  assign \$1391  = \fus_dest2_o$130  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1389 ;
-  assign \$1393  = \$1387  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1391 ;
-  assign \$1396  = \addr_en$1298  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1318 ;
-  assign \$1398  = \addr_en$1278  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1396 ;
-  assign \$1400  = \addr_en$1358  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1378 ;
-  assign \$1402  = \addr_en$1338  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1400 ;
-  assign \$1404  = \$1398  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1402 ;
-  assign \$1406  = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
-  assign \$1408  = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
-  assign \$1410  = \fus_cu_wr__rel_o$103 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$1412  = \fus_cu_wr__rel_o$112 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
-  assign \$1415  = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
-  assign \$1418  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1417 ;
-  assign \$1420  = \wr_pick$1414  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1418 ;
-  assign \$1423  = \wr_pick$1414  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
-  assign \$1426  = \wp$1422  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
-  assign \$1428  = \fus_xer_ca_ok$133  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$1431  = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
-  assign \$1434  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1433 ;
-  assign \$1436  = \wr_pick$1430  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1434 ;
-  assign \$1439  = \wr_pick$1430  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
-  assign \$1442  = \wp$1438  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
-  assign \$1444  = \fus_xer_ca_ok$134  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ;
-  assign \$1447  = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
-  assign \$1450  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1449 ;
-  assign \$1452  = \wr_pick$1446  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1450 ;
-  assign \$1455  = \wr_pick$1446  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
-  assign \$1458  = \wp$1454  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
-  assign \$1460  = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$136 ;
-  assign \$1462  = \fus_dest3_o$135  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1460 ;
-  assign \$1465  = \addr_en$1441  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1457 ;
-  assign \$1467  = \addr_en$1425  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1465 ;
-  assign \$1464  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1467 ;
-  assign \$1470  = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
-  assign \$1472  = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
-  assign \$1474  = \fus_cu_wr__rel_o$103 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$1476  = \fus_cu_wr__rel_o$106 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
-  assign \$1478  = \fus_cu_wr__rel_o$109 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
-  assign \$1481  = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
-  assign \$1484  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1483 ;
-  assign \$1486  = \wr_pick$1480  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1484 ;
-  assign \$1489  = \wr_pick$1480  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
-  assign \$1492  = \wp$1488  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
-  assign \$1494  = \fus_xer_ov_ok$137  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$1497  = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
-  assign \$1500  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1499 ;
-  assign \$1502  = \wr_pick$1496  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1500 ;
-  assign \$1505  = \wr_pick$1496  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
-  assign \$1508  = \wp$1504  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
-  assign \$1510  = \fus_xer_ov_ok$138  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ;
-  assign \$1513  = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
-  assign \$1516  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1515 ;
-  assign \$1518  = \wr_pick$1512  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1516 ;
-  assign \$1521  = \wr_pick$1512  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
-  assign \$1524  = \wp$1520  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
-  assign \$1526  = \fus_xer_ov_ok$139  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ;
-  assign \$1529  = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
-  assign \$1532  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1531 ;
-  assign \$1534  = \wr_pick$1528  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1532 ;
-  assign \$1537  = \wr_pick$1528  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
-  assign \$1540  = \wp$1536  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
-  assign \$1542  = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o;
-  assign \$1544  = \fus_dest3_o$140  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$141 ;
-  assign \$1546  = \$1542  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1544 ;
-  assign \$1548  = \addr_en$1491  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1507 ;
-  assign \$1550  = \addr_en$1523  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1539 ;
-  assign \$1552  = \$1548  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1550 ;
-  assign \$1554  = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
-  assign \$1556  = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
-  assign \$1558  = \fus_cu_wr__rel_o$103 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$1560  = \fus_cu_wr__rel_o$106 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
-  assign \$1562  = \fus_cu_wr__rel_o$109 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
-  assign \$1565  = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
-  assign \$1568  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1567 ;
-  assign \$1570  = \wr_pick$1564  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1568 ;
-  assign \$1573  = \wr_pick$1564  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
-  assign \$1576  = \wp$1572  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1578  = \fus_xer_so_ok$142  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$1581  = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
-  assign \$1584  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1583 ;
-  assign \$1586  = \wr_pick$1580  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1584 ;
-  assign \$1589  = \wr_pick$1580  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
-  assign \$1592  = \wp$1588  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1594  = \fus_xer_so_ok$143  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ;
-  assign \$1597  = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
-  assign \$1600  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1599 ;
-  assign \$1602  = \wr_pick$1596  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1600 ;
-  assign \$1605  = \wr_pick$1596  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
-  assign \$1608  = \wp$1604  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1610  = \fus_xer_so_ok$144  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ;
-  assign \$1613  = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
-  assign \$1616  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1615 ;
-  assign \$1618  = \wr_pick$1612  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1616 ;
-  assign \$1621  = \wr_pick$1612  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
-  assign \$1624  = \wp$1620  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1627  = \fus_dest5_o$145  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$146 ;
-  assign \$1629  = \fus_dest4_o$147  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$148 ;
-  assign \$1631  = \$1627  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1629 ;
-  assign \$1626  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1631 ;
-  assign \$1635  = \addr_en$1575  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1591 ;
-  assign \$1637  = \addr_en$1607  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1623 ;
-  assign \$1639  = \$1635  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1637 ;
-  assign \$1634  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1639 ;
-  assign \$1642  = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ;
-  assign \$1644  = \fus_cu_wr__rel_o$149 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
-  assign \$1646  = \fus_cu_wr__rel_o$97 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1648  = \fus_cu_wr__rel_o$103 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$1650  = \fus_cu_wr__rel_o$149 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
-  assign \$1652  = \fus_cu_wr__rel_o$97 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1654  = \fus_cu_wr__rel_o$97 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1657  = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1661  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1659 ;
-  assign \$1663  = \wr_pick$1656  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1661 ;
-  assign \$1668  = \wr_pick$1656  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1671  = \wp$1667  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
-  assign \$1673  = \fus_fast1_ok$151  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1676  = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1679  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1678 ;
-  assign \$1681  = \wr_pick$1675  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1679 ;
-  assign \$1684  = \wr_pick$1675  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1687  = \wp$1683  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
-  assign \$1689  = \fus_fast1_ok$152  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$1692  = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1695  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1694 ;
-  assign \$1697  = \wr_pick$1691  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1695 ;
-  assign \$1700  = \wr_pick$1691  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1703  = \wp$1699  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
-  assign \$1705  = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ;
-  assign \$1708  = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1711  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1710 ;
-  assign \$1713  = \wr_pick$1707  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1711 ;
-  assign \$1716  = \wr_pick$1707  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1719  = \wp$1715  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0;
-  assign \$1721  = \fus_fast2_ok$153  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1724  = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1727  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1726 ;
-  assign \$1729  = \wr_pick$1723  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1727 ;
-  assign \$1732  = \wr_pick$1723  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1735  = \wp$1731  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0;
-  assign \$1737  = fus_fast3_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1740  = wrpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
-  assign \$1743  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1742 ;
-  assign \$1745  = \wr_pick$1739  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1743 ;
-  assign \$1748  = \wr_pick$1739  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
-  assign \$1751  = \wp$1747  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto3 : 3'h0;
-  assign \$1753  = \fus_dest2_o$155  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$156 ;
-  assign \$1755  = \fus_dest1_o$154  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1753 ;
-  assign \$1757  = \fus_dest3_o$158  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$159 ;
-  assign \$1759  = \fus_dest2_o$157  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1757 ;
-  assign \$1761  = \$1755  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1759 ;
-  assign \$1764  = \addr_en$1686  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1702 ;
-  assign \$1766  = \addr_en$1670  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1764 ;
-  assign \$1768  = \addr_en$1734  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1750 ;
-  assign \$1770  = \addr_en$1718  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1768 ;
-  assign \$1772  = \$1766  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1770 ;
-  assign \$1763  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1772 ;
-  assign \$1775  = \wp$1683  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1699 ;
-  assign \$1777  = \wp$1667  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1775 ;
-  assign \$1779  = \wp$1731  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1747 ;
-  assign \$1781  = \wp$1715  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1779 ;
-  assign \$1783  = \$1777  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1781 ;
-  assign \$1785  = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ;
-  assign \$1787  = \fus_cu_wr__rel_o$149 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
-  assign \$1789  = \fus_cu_wr__rel_o$97 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1792  = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o;
-  assign \$1795  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1794 ;
-  assign \$1797  = \wr_pick$1791  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1795 ;
-  assign \$1800  = \wr_pick$1791  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o;
-  assign \$1803  = \wp$1799  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1805  = \fus_nia_ok$160  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1808  = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o;
-  assign \$1811  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1810 ;
-  assign \$1813  = \wr_pick$1807  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1811 ;
-  assign \$1816  = \wr_pick$1807  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o;
-  assign \$1819  = \wp$1815  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
-  assign \$1821  = \fus_dest3_o$161  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest5_o$162 ;
-  assign \$1824  = \addr_en$1802  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1818 ;
-  assign \$1823  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1824 ;
-  assign \$1827  = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1829  = \fus_cu_wr__rel_o$97 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1832  = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_msr_en_o;
-  assign \$1835  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1834 ;
-  assign \$1837  = \wr_pick$1831  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1835 ;
-  assign \$1840  = \wr_pick$1831  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_msr_en_o;
-  assign \$1843  = \wp$1839  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
-  assign \$1845  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) \addr_en$1842 ;
-  assign \$1847  = fus_svstate_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ;
-  assign \$1849  = \fus_cu_wr__rel_o$97 [6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$1852  = wrpick_STATE_svstate_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_svstate_en_o;
-  assign \$1855  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1854 ;
-  assign \$1857  = \wr_pick$1851  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1855 ;
-  assign \$1860  = \wr_pick$1851  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_svstate_en_o;
-  assign \$1863  = \wp$1859  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
-  assign \$1865  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) fus_dest7_o;
-  assign \$1867  = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ;
-  assign \$186  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 2'h2;
-  assign \$1869  = \fus_cu_wr__rel_o$103 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$1872  = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_SPR_spr1_en_o;
-  assign \$1875  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1874 ;
-  assign \$1877  = \wr_pick$1871  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1875 ;
-  assign \$185  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$186 ;
-  assign \$1880  = \wr_pick$1871  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_SPR_spr1_en_o;
-  assign \$1883  = \wp$1879  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_spro : 10'h000;
-  assign \$190  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 7'h40;
-  assign \$189  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$190 ;
-  assign \$194  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 6'h20;
-  assign \$193  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$194 ;
-  assign \$198  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 8'h80;
-  assign \$197  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$198 ;
-  assign \$202  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 5'h10;
-  assign \$201  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$202 ;
-  assign \$206  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 11'h400;
-  assign \$205  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$206 ;
-  assign \$210  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 10'h200;
-  assign \$209  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$210 ;
-  assign \$214  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 9'h100;
-  assign \$213  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$214 ;
-  assign \$218  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 4'h8;
-  assign \$217  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$218 ;
-  assign \$222  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 3'h4;
-  assign \$221  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$222 ;
-  assign \$225  = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0;
-  assign \$228  = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *) 1'h1;
-  assign \$230  = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0;
-  assign \$233  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
-  assign \$235  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$237  = \$235  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$239  = \$233  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$237 ;
-  assign \$241  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
-  assign \$243  = \$239  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$241 ;
-  assign \$245  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
-  assign \$247  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$249  = \$247  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$251  = \$245  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$249 ;
-  assign \$232  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$251 , \$243 , core_reg2_ok, core_reg1_ok };
-  assign \$254  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok };
-  assign \$256  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok };
-  assign \$258  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_fast3_ok, core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok };
+  wire [2:0] \xer_wen$159 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+  wire [2:0] \xer_wen$161 ;
+  assign \$999  = \wr_pick$992  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$997 ;
+  assign \$1004  = \wr_pick$992  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1007  = \wp$1003  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1009  = \fus_o_ok$89  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1012  = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1016  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1014 ;
+  assign \$1018  = \wr_pick$1011  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1016 ;
+  assign \$1027  = \wr_pick$1011  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1030  = \wp$1026  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1032  = \fus_o_ok$92  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$16 ;
+  assign \$1035  = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1039  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1037 ;
+  assign \$1041  = \wr_pick$1034  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1039 ;
+  assign \$1045  = \wr_pick$1034  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1048  = \wp$1044  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1050  = \fus_o_ok$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1053  = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1057  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1055 ;
+  assign \$1059  = \wr_pick$1052  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1057 ;
+  assign \$1067  = \wr_pick$1052  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1070  = \wp$1066  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1072  = \fus_o_ok$98  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$22 ;
+  assign \$1075  = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1079  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1077 ;
+  assign \$1081  = \wr_pick$1074  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1079 ;
+  assign \$1087  = \wr_pick$1074  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1090  = \wp$1086  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1092  = \fus_o_ok$101  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$25 ;
+  assign \$1095  = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1099  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1097 ;
+  assign \$1101  = \wr_pick$1094  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1099 ;
+  assign \$1107  = \wr_pick$1094  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1110  = \wp$1106  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1112  = \fus_o_ok$104  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$28 ;
+  assign \$1115  = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1119  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1117 ;
+  assign \$1121  = \wr_pick$1114  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1119 ;
+  assign \$1126  = \wr_pick$1114  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1129  = \wp$1125  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1131  = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$31 ;
+  assign \$1134  = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1138  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1136 ;
+  assign \$1140  = \wr_pick$1133  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1138 ;
+  assign \$1144  = \wr_pick$1133  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1147  = \wp$1143  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$1149  = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$31 ;
+  assign \$1152  = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$1155  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1154 ;
+  assign \$1157  = \wr_pick$1151  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1155 ;
+  assign \$1160  = \wr_pick$1151  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$1163  = \wp$1159  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_ea : 7'h00;
+  assign \$1166  = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$109 ;
+  assign \$1168  = \fus_dest1_o$111  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$112 ;
+  assign \$1170  = \fus_dest1_o$110  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1168 ;
+  assign \$1172  = \$1166  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1170 ;
+  assign \$1174  = \fus_dest1_o$113  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$114 ;
+  assign \$1176  = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea };
+  assign \$1178  = \fus_dest1_o$115  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1176 ;
+  assign \$1180  = \$1174  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1178 ;
+  assign \$1182  = \$1172  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1180 ;
+  assign \$1185  = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1006 ;
+  assign \$1187  = \addr_en$1047  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1069 ;
+  assign \$1189  = \addr_en$1029  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1187 ;
+  assign \$1191  = \$1185  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1189 ;
+  assign \$1193  = \addr_en$1089  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1109 ;
+  assign \$1195  = \addr_en$1146  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1162 ;
+  assign \$1197  = \addr_en$1128  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1195 ;
+  assign \$1199  = \$1193  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1197 ;
+  assign \$1201  = \$1191  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1199 ;
+  assign \$1203  = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1003 ;
+  assign \$1205  = \wp$1044  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1066 ;
+  assign \$1207  = \wp$1026  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ;
+  assign \$1209  = \$1203  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ;
+  assign \$1211  = \wp$1086  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1106 ;
+  assign \$1213  = \wp$1143  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1159 ;
+  assign \$1215  = \wp$1125  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1213 ;
+  assign \$1217  = \$1211  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1215 ;
+  assign \$1219  = \$1209  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1217 ;
+  assign \$1221  = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$7 ;
+  assign \$1223  = \fus_cu_wr__rel_o$87 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
+  assign \$1226  = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_full_cr_en_o;
+  assign \$1229  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1228 ;
+  assign \$1231  = \wr_pick$1225  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1229 ;
+  assign \$1234  = \wr_pick$1225  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_full_cr_en_o;
+  assign \$1237  = \wp$1233  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_core_cr_wr : 8'h00;
+  assign \$1239  = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
+  assign \$1241  = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
+  assign \$1243  = \fus_cu_wr__rel_o$87 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
+  assign \$1245  = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4];
+  assign \$1247  = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
+  assign \$1249  = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
+  assign \$1251  = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
+  assign \$1254  = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1257  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1256 ;
+  assign \$1259  = \wr_pick$1253  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1257 ;
+  assign \$1262  = \wr_pick$1253  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1265  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1267  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1265 ;
+  assign \$1269  = \wp$1261  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1267  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1271  = \fus_cr_a_ok$116  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$7 ;
+  assign \$1274  = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1277  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1276 ;
+  assign \$1279  = \wr_pick$1273  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1277 ;
+  assign \$1282  = \wr_pick$1273  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1285  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1287  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1285 ;
+  assign \$1289  = \wp$1281  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1287  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1291  = \fus_cr_a_ok$117  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$16 ;
+  assign \$1294  = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1297  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1296 ;
+  assign \$1299  = \wr_pick$1293  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1297 ;
+  assign \$1302  = \wr_pick$1293  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1305  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1307  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1305 ;
+  assign \$1309  = \wp$1301  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1307  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1311  = \fus_cr_a_ok$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$22 ;
+  assign \$1314  = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1317  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1316 ;
+  assign \$1319  = \wr_pick$1313  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1317 ;
+  assign \$1322  = \wr_pick$1313  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1325  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1327  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1325 ;
+  assign \$1329  = \wp$1321  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1327  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1331  = \fus_cr_a_ok$119  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$25 ;
+  assign \$1334  = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1337  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1336 ;
+  assign \$1339  = \wr_pick$1333  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1337 ;
+  assign \$1342  = \wr_pick$1333  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1345  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1347  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1345 ;
+  assign \$1349  = \wp$1341  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1347  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1351  = \fus_cr_a_ok$120  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$28 ;
+  assign \$1354  = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o;
+  assign \$1357  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1356 ;
+  assign \$1359  = \wr_pick$1353  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1357 ;
+  assign \$1362  = \wr_pick$1353  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o;
+  assign \$1365  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out;
+  assign \$1367  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1365 ;
+  assign \$1369  = \wp$1361  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1367  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$1371  = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$122 ;
+  assign \$1373  = \fus_dest2_o$121  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1371 ;
+  assign \$1375  = \fus_dest2_o$124  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$125 ;
+  assign \$1377  = \fus_dest2_o$123  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1375 ;
+  assign \$1379  = \$1373  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1377 ;
+  assign \$1382  = \addr_en$1284  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1304 ;
+  assign \$1384  = \addr_en$1264  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1382 ;
+  assign \$1386  = \addr_en$1344  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1364 ;
+  assign \$1388  = \addr_en$1324  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1386 ;
+  assign \$1390  = \$1384  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1388 ;
+  assign \$1392  = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
+  assign \$1394  = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
+  assign \$1396  = \fus_cu_wr__rel_o$96 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$1398  = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
+  assign \$1401  = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
+  assign \$1404  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1403 ;
+  assign \$1406  = \wr_pick$1400  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1404 ;
+  assign \$1409  = \wr_pick$1400  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
+  assign \$1412  = \wp$1408  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
+  assign \$1414  = \fus_xer_ca_ok$126  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1417  = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
+  assign \$1420  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1419 ;
+  assign \$1422  = \wr_pick$1416  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1420 ;
+  assign \$1425  = \wr_pick$1416  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
+  assign \$1428  = \wp$1424  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
+  assign \$1430  = \fus_xer_ca_ok$127  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$28 ;
+  assign \$1433  = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o;
+  assign \$1436  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1435 ;
+  assign \$1438  = \wr_pick$1432  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1436 ;
+  assign \$1441  = \wr_pick$1432  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o;
+  assign \$1444  = \wp$1440  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
+  assign \$1446  = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$129 ;
+  assign \$1448  = \fus_dest3_o$128  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1446 ;
+  assign \$1451  = \addr_en$1427  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1443 ;
+  assign \$1453  = \addr_en$1411  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1451 ;
+  assign \$1450  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1453 ;
+  assign \$1456  = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
+  assign \$1458  = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
+  assign \$1460  = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$1462  = \fus_cu_wr__rel_o$99 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
+  assign \$1464  = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
+  assign \$1467  = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
+  assign \$1470  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1469 ;
+  assign \$1472  = \wr_pick$1466  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1470 ;
+  assign \$1475  = \wr_pick$1466  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
+  assign \$1478  = \wp$1474  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
+  assign \$1480  = \fus_xer_ov_ok$130  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1483  = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
+  assign \$1486  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1485 ;
+  assign \$1488  = \wr_pick$1482  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1486 ;
+  assign \$1491  = \wr_pick$1482  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
+  assign \$1494  = \wp$1490  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
+  assign \$1496  = \fus_xer_ov_ok$131  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$22 ;
+  assign \$1499  = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
+  assign \$1502  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1501 ;
+  assign \$1504  = \wr_pick$1498  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1502 ;
+  assign \$1507  = \wr_pick$1498  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
+  assign \$1510  = \wp$1506  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
+  assign \$1512  = \fus_xer_ov_ok$132  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$25 ;
+  assign \$1515  = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o;
+  assign \$1518  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1517 ;
+  assign \$1520  = \wr_pick$1514  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1518 ;
+  assign \$1523  = \wr_pick$1514  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o;
+  assign \$1526  = \wp$1522  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
+  assign \$1528  = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o;
+  assign \$1530  = \fus_dest3_o$133  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$134 ;
+  assign \$1532  = \$1528  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1530 ;
+  assign \$1534  = \addr_en$1477  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1493 ;
+  assign \$1536  = \addr_en$1509  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1525 ;
+  assign \$1538  = \$1534  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1536 ;
+  assign \$1540  = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
+  assign \$1542  = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
+  assign \$1544  = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$1546  = \fus_cu_wr__rel_o$99 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
+  assign \$1548  = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
+  assign \$1551  = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
+  assign \$1554  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1553 ;
+  assign \$1556  = \wr_pick$1550  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1554 ;
+  assign \$1559  = \wr_pick$1550  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
+  assign \$1562  = \wp$1558  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1564  = \fus_xer_so_ok$135  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1567  = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
+  assign \$1570  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1569 ;
+  assign \$1572  = \wr_pick$1566  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1570 ;
+  assign \$1575  = \wr_pick$1566  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
+  assign \$1578  = \wp$1574  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1580  = \fus_xer_so_ok$136  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$22 ;
+  assign \$1583  = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
+  assign \$1586  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1585 ;
+  assign \$1588  = \wr_pick$1582  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1586 ;
+  assign \$1591  = \wr_pick$1582  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
+  assign \$1594  = \wp$1590  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1596  = \fus_xer_so_ok$137  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$25 ;
+  assign \$1599  = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o;
+  assign \$1602  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1601 ;
+  assign \$1604  = \wr_pick$1598  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1602 ;
+  assign \$1607  = \wr_pick$1598  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o;
+  assign \$1610  = \wp$1606  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1613  = \fus_dest5_o$138  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$139 ;
+  assign \$1615  = \fus_dest4_o$140  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$141 ;
+  assign \$1617  = \$1613  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ;
+  assign \$1612  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ;
+  assign \$1621  = \addr_en$1561  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1577 ;
+  assign \$1623  = \addr_en$1593  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1609 ;
+  assign \$1625  = \$1621  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1623 ;
+  assign \$1620  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1625 ;
+  assign \$1628  = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$10 ;
+  assign \$1630  = \fus_cu_wr__rel_o$142 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
+  assign \$1632  = \fus_cu_wr__rel_o$90 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1634  = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$1636  = \fus_cu_wr__rel_o$142 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
+  assign \$1638  = \fus_cu_wr__rel_o$90 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1640  = \fus_cu_wr__rel_o$90 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1643  = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$1647  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1645 ;
+  assign \$1649  = \wr_pick$1642  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1647 ;
+  assign \$1654  = \wr_pick$1642  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1657  = \wp$1653  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
+  assign \$1659  = \fus_fast1_ok$144  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1662  = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$1665  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1664 ;
+  assign \$1667  = \wr_pick$1661  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1665 ;
+  assign \$1670  = \wr_pick$1661  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1673  = \wp$1669  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
+  assign \$1675  = \fus_fast1_ok$145  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1678  = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$1681  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1680 ;
+  assign \$1683  = \wr_pick$1677  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1681 ;
+  assign \$1686  = \wr_pick$1677  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1689  = \wp$1685  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0;
+  assign \$1691  = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$10 ;
+  assign \$1694  = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$1697  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1696 ;
+  assign \$1699  = \wr_pick$1693  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1697 ;
+  assign \$1702  = \wr_pick$1693  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1705  = \wp$1701  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0;
+  assign \$1707  = \fus_fast2_ok$146  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1710  = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$1713  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1712 ;
+  assign \$1715  = \wr_pick$1709  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1713 ;
+  assign \$1718  = \wr_pick$1709  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1721  = \wp$1717  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0;
+  assign \$1723  = fus_fast3_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1726  = wrpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o;
+  assign \$172  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 2'h2;
+  assign \$1729  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1728 ;
+  assign \$1731  = \wr_pick$1725  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1729 ;
+  assign \$1734  = \wr_pick$1725  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o;
+  assign \$1737  = \wp$1733  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto3 : 3'h0;
+  assign \$171  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$172 ;
+  assign \$1739  = \fus_dest2_o$148  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$149 ;
+  assign \$1741  = \fus_dest1_o$147  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1739 ;
+  assign \$1743  = \fus_dest3_o$151  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$152 ;
+  assign \$1745  = \fus_dest2_o$150  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1743 ;
+  assign \$1747  = \$1741  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1745 ;
+  assign \$1750  = \addr_en$1672  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1688 ;
+  assign \$1752  = \addr_en$1656  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1750 ;
+  assign \$1754  = \addr_en$1720  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1736 ;
+  assign \$1756  = \addr_en$1704  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1754 ;
+  assign \$1758  = \$1752  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1756 ;
+  assign \$1749  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1758 ;
+  assign \$1761  = \wp$1669  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1685 ;
+  assign \$1763  = \wp$1653  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1761 ;
+  assign \$1765  = \wp$1717  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1733 ;
+  assign \$1767  = \wp$1701  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1765 ;
+  assign \$176  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 7'h40;
+  assign \$1769  = \$1763  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1767 ;
+  assign \$1771  = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$10 ;
+  assign \$1773  = \fus_cu_wr__rel_o$142 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2];
+  assign \$1775  = \fus_cu_wr__rel_o$90 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1778  = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o;
+  assign \$175  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$176 ;
+  assign \$1781  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1780 ;
+  assign \$1783  = \wr_pick$1777  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1781 ;
+  assign \$1786  = \wr_pick$1777  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o;
+  assign \$1789  = \wp$1785  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1791  = \fus_nia_ok$153  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1794  = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o;
+  assign \$1797  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1796 ;
+  assign \$1799  = \wr_pick$1793  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1797 ;
+  assign \$1802  = \wr_pick$1793  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o;
+  assign \$1805  = \wp$1801  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0;
+  assign \$1807  = \fus_dest3_o$154  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest5_o$155 ;
+  assign \$180  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 6'h20;
+  assign \$1810  = \addr_en$1788  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1804 ;
+  assign \$1809  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1810 ;
+  assign \$1813  = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1815  = \fus_cu_wr__rel_o$90 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1818  = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_msr_en_o;
+  assign \$179  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$180 ;
+  assign \$1821  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1820 ;
+  assign \$1823  = \wr_pick$1817  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1821 ;
+  assign \$1826  = \wr_pick$1817  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_msr_en_o;
+  assign \$1829  = \wp$1825  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0;
+  assign \$1831  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) \addr_en$1828 ;
+  assign \$1833  = fus_svstate_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$13 ;
+  assign \$1835  = \fus_cu_wr__rel_o$90 [6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$1838  = wrpick_STATE_svstate_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_svstate_en_o;
+  assign \$1841  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1840 ;
+  assign \$1843  = \wr_pick$1837  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1841 ;
+  assign \$1846  = \wr_pick$1837  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_svstate_en_o;
+  assign \$184  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 8'h80;
+  assign \$1849  = \wp$1845  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0;
+  assign \$1851  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) fus_dest7_o;
+  assign \$1853  = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$19 ;
+  assign \$1855  = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$1858  = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_SPR_spr1_en_o;
+  assign \$183  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$184 ;
+  assign \$1861  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1860 ;
+  assign \$1863  = \wr_pick$1857  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1861 ;
+  assign \$1866  = \wr_pick$1857  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_SPR_spr1_en_o;
+  assign \$1869  = \wp$1865  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_spro : 10'h000;
+  assign \$188  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 5'h10;
+  assign \$187  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$188 ;
+  assign \$192  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 11'h400;
+  assign \$191  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$192 ;
+  assign \$196  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 10'h200;
+  assign \$195  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$196 ;
+  assign \$200  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 9'h100;
+  assign \$199  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$200 ;
+  assign \$204  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 4'h8;
+  assign \$203  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$204 ;
+  assign \$208  = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 3'h4;
+  assign \$207  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$208 ;
+  assign \$211  = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0;
+  assign \$214  = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *) 1'h1;
+  assign \$216  = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0;
+  assign \$219  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
+  assign \$221  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$223  = \$221  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$225  = \$219  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$223 ;
+  assign \$227  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
+  assign \$229  = \$225  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$227 ;
+  assign \$231  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
+  assign \$233  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$235  = \$233  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$237  = \$231  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$235 ;
+  assign \$218  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$237 , \$229 , core_reg2_ok, core_reg1_ok };
+  assign \$240  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok };
+  assign \$242  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok };
+  assign \$244  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_fast3_ok, core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok };
+  assign \$247  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
+  assign \$249  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$251  = \$249  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$253  = \$247  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$251 ;
+  assign \$255  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
+  assign \$257  = \$253  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$255 ;
+  assign \$246  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$257 , core_reg2_ok, core_reg1_ok };
   assign \$261  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
   assign \$263  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
   assign \$265  = \$263  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
   assign \$267  = \$261  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$265 ;
   assign \$269  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
   assign \$271  = \$267  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$269 ;
-  assign \$260  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$271 , core_reg2_ok, core_reg1_ok };
-  assign \$275  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
-  assign \$277  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$279  = \$277  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$281  = \$275  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$279 ;
-  assign \$283  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
-  assign \$285  = \$281  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$283 ;
-  assign \$287  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
-  assign \$289  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
-  assign \$291  = \$289  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
-  assign \$293  = \$287  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$291 ;
-  assign \$295  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
-  assign \$297  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$299  = \$297  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$301  = \$295  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$299 ;
-  assign \$274  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$301 , \$293 , \$285 , core_fast1_ok, core_spr1_ok, core_reg1_ok };
+  assign \$273  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
+  assign \$275  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
+  assign \$277  = \$275  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
+  assign \$279  = \$273  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$277 ;
+  assign \$281  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
+  assign \$283  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$285  = \$283  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$287  = \$281  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$285 ;
+  assign \$260  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$287 , \$279 , \$271 , core_fast1_ok, core_spr1_ok, core_reg1_ok };
+  assign \$291  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
+  assign \$293  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$295  = \$293  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$297  = \$291  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$295 ;
+  assign \$299  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
+  assign \$301  = \$297  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$299 ;
+  assign \$290  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$301 , core_reg2_ok, core_reg1_ok };
   assign \$305  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
   assign \$307  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
   assign \$309  = \$307  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
@@ -45866,414 +45868,412 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   assign \$325  = \$319  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$323 ;
   assign \$327  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
   assign \$329  = \$325  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$327 ;
-  assign \$318  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$329 , core_reg2_ok, core_reg1_ok };
-  assign \$333  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
-  assign \$335  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$337  = \$335  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$339  = \$333  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$337 ;
-  assign \$341  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
-  assign \$343  = \$339  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$341 ;
-  assign \$345  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
-  assign \$347  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$349  = \$347  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$351  = \$345  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$349 ;
-  assign \$332  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$351 , \$343 , core_reg3_ok, core_reg2_ok, core_reg1_ok };
-  assign \$354  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok };
-  assign \$356  = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
-  assign \$358  = \$356  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$360  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_0;
-  assign \$362  = \$358  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$360 ;
-  assign \$364  = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$366  = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$368  = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$370  = \$368  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$372  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_1;
-  assign \$374  = \$370  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$372 ;
-  assign \$376  = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$378  = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$380  = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
-  assign \$382  = \$380  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$384  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_2;
-  assign \$386  = \$382  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$384 ;
-  assign \$388  = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$390  = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$392  = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
-  assign \$394  = \$392  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$396  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_3;
-  assign \$398  = \$394  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$396 ;
-  assign \$400  = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$402  = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$404  = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
-  assign \$406  = \$404  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$408  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_4;
-  assign \$410  = \$406  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$408 ;
-  assign \$412  = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$414  = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$416  = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
-  assign \$418  = \$416  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$420  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_5;
-  assign \$422  = \$418  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$420 ;
-  assign \$424  = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$426  = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$428  = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
-  assign \$430  = \$428  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$432  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_6;
-  assign \$434  = \$430  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$432 ;
-  assign \$436  = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$438  = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$440  = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
-  assign \$442  = \$440  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
-  assign \$444  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_7;
-  assign \$446  = \$442  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$444 ;
-  assign \$448  = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$450  = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
-  assign \$452  = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
-  assign \$454  = \$452  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1;
-  assign \$456  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_8;
-  assign \$458  = \$454  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$456 ;
-  assign \$460  = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$462  = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00;
-  assign \$464  = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
-  assign \$466  = \$464  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1;
-  assign \$468  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_9;
-  assign \$470  = \$466  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$468 ;
-  assign \$472  = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$474  = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00;
-  assign \$476  = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
-  assign \$478  = \$476  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$480  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_10;
-  assign \$482  = \$478  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$480 ;
-  assign \$484  = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$486  = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$488  = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$490  = \$488  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$492  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_11;
-  assign \$494  = \$490  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$492 ;
-  assign \$496  = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$498  = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$500  = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
-  assign \$502  = \$500  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$504  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_12;
-  assign \$506  = \$502  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$504 ;
-  assign \$508  = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$510  = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$512  = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
-  assign \$514  = \$512  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$516  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_13;
-  assign \$518  = \$514  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$516 ;
-  assign \$520  = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$522  = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$524  = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$526  = \$524  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$528  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_spr0_14;
-  assign \$530  = \$526  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$528 ;
-  assign \$532  = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$534  = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$536  = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
-  assign \$538  = \$536  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$540  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_15;
-  assign \$542  = \$538  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$540 ;
-  assign \$544  = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$546  = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$548  = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
-  assign \$550  = \$548  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$552  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_16;
-  assign \$554  = \$550  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$552 ;
-  assign \$556  = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$558  = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$560  = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
-  assign \$562  = \$560  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$564  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_17;
-  assign \$566  = \$562  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$564 ;
-  assign \$568  = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$570  = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$572  = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
-  assign \$574  = \$572  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
-  assign \$576  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_18;
-  assign \$578  = \$574  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$576 ;
-  assign \$580  = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
-  assign \$582  = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
-  assign \$585  = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1;
-  assign \$587  = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3;
-  assign \$589  = \$585  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$587 ;
-  assign \$591  = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5;
-  assign \$593  = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8;
-  assign \$595  = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$593 ;
-  assign \$597  = \$591  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$595 ;
-  assign \$599  = \$589  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$597 ;
-  assign \$601  = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10;
-  assign \$603  = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13;
-  assign \$605  = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$603 ;
-  assign \$607  = \$601  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$605 ;
-  assign \$609  = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15;
-  assign \$611  = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18;
-  assign \$613  = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ;
-  assign \$615  = \$609  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ;
-  assign \$617  = \$607  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$615 ;
-  assign \$619  = \$599  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$617 ;
-  assign \$621  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 };
-  assign \$623  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
-  assign \$625  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$627  = \$625  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
-  assign \$629  = \$623  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$627 ;
-  assign \$631  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
-  assign \$633  = \$629  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$631 ;
-  assign \$635  = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
-  assign \$637  = \$635  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$639  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_alu0_0;
-  assign \$641  = \$637  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$639 ;
-  assign \$643  = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$645  = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$647  = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
-  assign \$649  = \$647  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$651  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_logical0_1;
-  assign \$653  = \$649  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$651 ;
-  assign \$655  = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$657  = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$659  = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$661  = \$659  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$663  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_spr0_2;
-  assign \$665  = \$661  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$663 ;
-  assign \$667  = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$669  = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$671  = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
-  assign \$673  = \$671  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$675  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_div0_3;
-  assign \$677  = \$673  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$675 ;
-  assign \$679  = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$681  = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$683  = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
-  assign \$685  = \$683  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$687  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_mul0_4;
-  assign \$689  = \$685  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$687 ;
-  assign \$691  = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$693  = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$695  = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
-  assign \$697  = \$695  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
-  assign \$699  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_shiftrot0_5;
-  assign \$701  = \$697  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$699 ;
-  assign \$703  = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
-  assign \$705  = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
-  assign \$708  = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2;
-  assign \$710  = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ;
-  assign \$712  = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5;
-  assign \$714  = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ;
-  assign \$716  = \$710  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$714 ;
-  assign \$707  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$716 ;
-  assign \$719  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
-  assign \$721  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$723  = \$721  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
-  assign \$725  = \$719  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$723 ;
-  assign \$727  = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
-  assign \$729  = \$727  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
-  assign \$731  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_alu0_0;
-  assign \$733  = \$729  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$731 ;
-  assign \$735  = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
-  assign \$737  = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
-  assign \$739  = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$741  = \$739  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
-  assign \$743  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_spr0_1;
-  assign \$745  = \$741  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$743 ;
-  assign \$747  = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
-  assign \$749  = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
-  assign \$751  = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
-  assign \$753  = \$751  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
-  assign \$755  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_shiftrot0_2;
-  assign \$757  = \$753  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$755 ;
-  assign \$759  = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
-  assign \$761  = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
-  assign \$764  = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2;
-  assign \$766  = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$764 ;
-  assign \$763  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$766 ;
-  assign \$769  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
-  assign \$771  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
-  assign \$773  = \$771  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
-  assign \$775  = \$769  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$773 ;
-  assign \$777  = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$779  = \$777  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ov_0;
-  assign \$781  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ov_spr0_0;
-  assign \$783  = \$779  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$781 ;
-  assign \$785  = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ov_en_o;
-  assign \$787  = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 3'h4 : 3'h0;
-  assign \$789  = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$791  = \$789  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_full_cr_0;
-  assign \$793  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_full_cr_cr0_0;
-  assign \$795  = \$791  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$793 ;
-  assign \$797  = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_full_cr_en_o;
-  assign \$799  = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_core_cr_rd : 8'h00;
-  assign \$801  = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$803  = \$801  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0;
-  assign \$805  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_cr0_0;
-  assign \$807  = \$803  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$805 ;
-  assign \$809  = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o;
-  assign \$811  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1;
-  assign \$813  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$811 ;
-  assign \$815  = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$813  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$817  = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
-  assign \$819  = \$817  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0;
-  assign \$821  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_branch0_1;
-  assign \$823  = \$819  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$821 ;
-  assign \$825  = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o;
-  assign \$827  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1;
-  assign \$829  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$827 ;
-  assign \$831  = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$829  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$834  = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1;
-  assign \$836  = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$838  = \$836  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_b_0;
-  assign \$840  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_b_cr0_0;
-  assign \$842  = \$838  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$840 ;
-  assign \$844  = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_b_en_o;
-  assign \$846  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) core_cr_in2;
-  assign \$848  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) \$846 ;
-  assign \$850  = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$848  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$852  = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
-  assign \$854  = \$852  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_c_0;
-  assign \$856  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_c_cr0_0;
-  assign \$858  = \$854  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$856 ;
-  assign \$860  = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_c_en_o;
-  assign \$862  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ;
-  assign \$864  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \$862 ;
-  assign \$866  = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$864  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
-  assign \$868  = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
-  assign \$870  = \$868  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
-  assign \$872  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_0;
-  assign \$874  = \$870  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$872 ;
-  assign \$876  = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$878  = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
-  assign \$880  = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
-  assign \$882  = \$880  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
-  assign \$884  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_1;
-  assign \$886  = \$882  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$884 ;
-  assign \$888  = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$890  = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
-  assign \$892  = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$894  = \$892  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
-  assign \$896  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_spr0_2;
-  assign \$898  = \$894  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$896 ;
-  assign \$900  = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$902  = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
-  assign \$904  = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
-  assign \$906  = \$904  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1;
-  assign \$908  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_3;
-  assign \$910  = \$906  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$908 ;
-  assign \$912  = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$914  = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0;
-  assign \$916  = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
-  assign \$918  = \$916  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1;
-  assign \$920  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_4;
-  assign \$922  = \$918  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$920 ;
-  assign \$924  = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$926  = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0;
-  assign \$928  = \fus_cu_rd__rel_o$43 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
-  assign \$930  = \$928  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_2;
-  assign \$932  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_5;
-  assign \$934  = \$930  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$932 ;
-  assign \$936  = rdpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
-  assign \$938  = rp_FAST_fast1_trap0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast3 : 3'h0;
-  assign \$941  = addr_en_FAST_fast1_trap0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_spr0_2;
-  assign \$943  = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$941 ;
-  assign \$945  = addr_en_FAST_fast1_trap0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_5;
-  assign \$947  = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$945 ;
-  assign \$949  = \$943  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$947 ;
-  assign \$940  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$949 ;
-  assign \$952  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_FAST_fast1_trap0_5, rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 };
-  assign \$954  = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
-  assign \$956  = \$954  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_SPR_spr1_0;
-  assign \$958  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_SPR_spr1_spr0_0;
-  assign \$960  = \$956  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$958 ;
-  assign \$962  = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_SPR_spr1_en_o;
-  assign \$964  = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_spr1 : 10'h000;
-  assign \$966  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) rp_SPR_spr1_spr0_0;
-  assign \$968  = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
-  assign \$970  = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
-  assign \$972  = \fus_cu_wr__rel_o$94 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
-  assign \$974  = \fus_cu_wr__rel_o$97 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
-  assign \$976  = \fus_cu_wr__rel_o$100 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4];
-  assign \$978  = \fus_cu_wr__rel_o$103 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
-  assign \$980  = \fus_cu_wr__rel_o$106 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
-  assign \$982  = \fus_cu_wr__rel_o$109 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
-  assign \$984  = \fus_cu_wr__rel_o$112 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
-  assign \$986  = \fus_cu_wr__rel_o$114 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9];
-  assign \$988  = \fus_cu_wr__rel_o$114 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9];
-  assign \$990  = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
-  assign \$992  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly;
-  assign \$994  = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$992 ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1874  <= \wr_pick_dly$1874$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1854  <= \wr_pick_dly$1854$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1834  <= \wr_pick_dly$1834$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1810  <= \wr_pick_dly$1810$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1794  <= \wr_pick_dly$1794$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1742  <= \wr_pick_dly$1742$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1726  <= \wr_pick_dly$1726$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1710  <= \wr_pick_dly$1710$next ;
-  always @(posedge coresync_clk)
-    \wr_pick_dly$1694  <= \wr_pick_dly$1694$next ;
+  assign \$331  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
+  assign \$333  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$335  = \$333  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$337  = \$331  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$335 ;
+  assign \$318  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$337 , \$329 , core_reg3_ok, core_reg2_ok, core_reg1_ok };
+  assign \$340  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok };
+  assign \$342  = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
+  assign \$344  = \$342  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$346  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_0;
+  assign \$348  = \$344  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$346 ;
+  assign \$350  = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$352  = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$354  = \fus_cu_rd__rel_o$33 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$356  = \$354  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$358  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_1;
+  assign \$360  = \$356  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$358 ;
+  assign \$362  = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$364  = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$366  = \fus_cu_rd__rel_o$36 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
+  assign \$368  = \$366  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$370  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_2;
+  assign \$372  = \$368  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$370 ;
+  assign \$374  = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$376  = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$378  = \fus_cu_rd__rel_o$39 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
+  assign \$380  = \$378  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$382  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_3;
+  assign \$384  = \$380  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$382 ;
+  assign \$386  = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$388  = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$390  = \fus_cu_rd__rel_o$42 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
+  assign \$392  = \$390  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$394  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_4;
+  assign \$396  = \$392  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$394 ;
+  assign \$398  = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$400  = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$402  = \fus_cu_rd__rel_o$45 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
+  assign \$404  = \$402  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$406  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_5;
+  assign \$408  = \$404  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$406 ;
+  assign \$410  = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$412  = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$414  = \fus_cu_rd__rel_o$48 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
+  assign \$416  = \$414  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$418  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_6;
+  assign \$420  = \$416  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$418 ;
+  assign \$422  = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$424  = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$426  = \fus_cu_rd__rel_o$51 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
+  assign \$428  = \$426  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0;
+  assign \$430  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_7;
+  assign \$432  = \$428  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$430 ;
+  assign \$434  = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$436  = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00;
+  assign \$438  = \fus_cu_rd__rel_o$48 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
+  assign \$440  = \$438  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1;
+  assign \$442  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_8;
+  assign \$444  = \$440  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$442 ;
+  assign \$446  = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$448  = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00;
+  assign \$450  = \fus_cu_rd__rel_o$51 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
+  assign \$452  = \$450  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1;
+  assign \$454  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_9;
+  assign \$456  = \$452  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$454 ;
+  assign \$458  = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$460  = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00;
+  assign \$462  = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
+  assign \$464  = \$462  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$466  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_10;
+  assign \$468  = \$464  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$466 ;
+  assign \$470  = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$472  = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$474  = \fus_cu_rd__rel_o$33 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$476  = \$474  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$478  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_11;
+  assign \$480  = \$476  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$478 ;
+  assign \$482  = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$484  = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$486  = \fus_cu_rd__rel_o$36 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
+  assign \$488  = \$486  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$490  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_12;
+  assign \$492  = \$488  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$490 ;
+  assign \$494  = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$496  = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$498  = \fus_cu_rd__rel_o$39 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
+  assign \$500  = \$498  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$502  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_13;
+  assign \$504  = \$500  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$502 ;
+  assign \$506  = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$508  = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$510  = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$512  = \$510  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$514  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_spr0_14;
+  assign \$516  = \$512  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$514 ;
+  assign \$518  = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$520  = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$522  = \fus_cu_rd__rel_o$42 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
+  assign \$524  = \$522  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$526  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_15;
+  assign \$528  = \$524  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$526 ;
+  assign \$530  = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$532  = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$534  = \fus_cu_rd__rel_o$45 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
+  assign \$536  = \$534  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$538  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_16;
+  assign \$540  = \$536  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$538 ;
+  assign \$542  = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$544  = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$546  = \fus_cu_rd__rel_o$48 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
+  assign \$548  = \$546  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$550  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_17;
+  assign \$552  = \$548  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$550 ;
+  assign \$554  = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$556  = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$558  = \fus_cu_rd__rel_o$51 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9];
+  assign \$560  = \$558  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2;
+  assign \$562  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_18;
+  assign \$564  = \$560  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$562 ;
+  assign \$566  = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o;
+  assign \$568  = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00;
+  assign \$571  = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1;
+  assign \$573  = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3;
+  assign \$575  = \$571  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$573 ;
+  assign \$577  = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5;
+  assign \$579  = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8;
+  assign \$581  = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$579 ;
+  assign \$583  = \$577  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$581 ;
+  assign \$585  = \$575  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ;
+  assign \$587  = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10;
+  assign \$589  = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13;
+  assign \$591  = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$589 ;
+  assign \$593  = \$587  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$591 ;
+  assign \$595  = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15;
+  assign \$597  = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18;
+  assign \$599  = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$597 ;
+  assign \$601  = \$595  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$599 ;
+  assign \$603  = \$593  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$601 ;
+  assign \$605  = \$585  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$603 ;
+  assign \$607  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 };
+  assign \$609  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
+  assign \$611  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$613  = \$611  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1;
+  assign \$615  = \$609  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$613 ;
+  assign \$617  = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
+  assign \$619  = \$615  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$617 ;
+  assign \$621  = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
+  assign \$623  = \$621  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$625  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_alu0_0;
+  assign \$627  = \$623  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$625 ;
+  assign \$629  = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$631  = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$633  = \fus_cu_rd__rel_o$39 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4];
+  assign \$635  = \$633  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$637  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_logical0_1;
+  assign \$639  = \$635  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$637 ;
+  assign \$641  = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$643  = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$645  = \fus_cu_rd__rel_o$58 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$647  = \$645  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$649  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_spr0_2;
+  assign \$651  = \$647  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$649 ;
+  assign \$653  = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$655  = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$657  = \fus_cu_rd__rel_o$42 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6];
+  assign \$659  = \$657  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$661  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_div0_3;
+  assign \$663  = \$659  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$661 ;
+  assign \$665  = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$667  = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$669  = \fus_cu_rd__rel_o$45 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7];
+  assign \$671  = \$669  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$673  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_mul0_4;
+  assign \$675  = \$671  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$673 ;
+  assign \$677  = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$679  = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$681  = \fus_cu_rd__rel_o$48 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
+  assign \$683  = \$681  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0;
+  assign \$685  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_shiftrot0_5;
+  assign \$687  = \$683  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$685 ;
+  assign \$689  = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o;
+  assign \$691  = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0;
+  assign \$694  = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2;
+  assign \$696  = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$694 ;
+  assign \$698  = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5;
+  assign \$700  = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$698 ;
+  assign \$702  = \$696  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$700 ;
+  assign \$693  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$702 ;
+  assign \$705  = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2;
+  assign \$707  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$709  = \$707  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4;
+  assign \$711  = \$705  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$709 ;
+  assign \$713  = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0];
+  assign \$715  = \$713  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
+  assign \$717  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_alu0_0;
+  assign \$719  = \$715  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$717 ;
+  assign \$721  = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
+  assign \$723  = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
+  assign \$725  = \fus_cu_rd__rel_o$58 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$727  = \$725  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
+  assign \$729  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_spr0_1;
+  assign \$731  = \$727  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$729 ;
+  assign \$733  = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
+  assign \$735  = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
+  assign \$737  = \fus_cu_rd__rel_o$48 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8];
+  assign \$739  = \$737  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0;
+  assign \$741  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_shiftrot0_2;
+  assign \$743  = \$739  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$741 ;
+  assign \$745  = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o;
+  assign \$747  = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0;
+  assign \$750  = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2;
+  assign \$752  = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$750 ;
+  assign \$749  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$752 ;
+  assign \$755  = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
+  assign \$757  = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
+  assign \$759  = \$757  == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2;
+  assign \$761  = \$755  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$759 ;
+  assign \$763  = \fus_cu_rd__rel_o$58 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$765  = \$763  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ov_0;
+  assign \$767  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ov_spr0_0;
+  assign \$769  = \$765  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$767 ;
+  assign \$771  = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ov_en_o;
+  assign \$773  = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 3'h4 : 3'h0;
+  assign \$775  = \fus_cu_rd__rel_o$33 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$777  = \$775  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_full_cr_0;
+  assign \$779  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_full_cr_cr0_0;
+  assign \$781  = \$777  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$779 ;
+  assign \$783  = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_full_cr_en_o;
+  assign \$785  = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_core_cr_rd : 8'h00;
+  assign \$787  = \fus_cu_rd__rel_o$33 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$789  = \$787  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0;
+  assign \$791  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_cr0_0;
+  assign \$793  = \$789  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$791 ;
+  assign \$795  = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o;
+  assign \$797  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1;
+  assign \$799  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$797 ;
+  assign \$801  = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$799  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$803  = \fus_cu_rd__rel_o$74 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
+  assign \$805  = \$803  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0;
+  assign \$807  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_branch0_1;
+  assign \$809  = \$805  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$807 ;
+  assign \$811  = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o;
+  assign \$813  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1;
+  assign \$815  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$813 ;
+  assign \$817  = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$815  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$820  = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1;
+  assign \$822  = \fus_cu_rd__rel_o$33 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$824  = \$822  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_b_0;
+  assign \$826  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_b_cr0_0;
+  assign \$828  = \$824  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$826 ;
+  assign \$830  = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_b_en_o;
+  assign \$832  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) core_cr_in2;
+  assign \$834  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) \$832 ;
+  assign \$836  = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$834  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$838  = \fus_cu_rd__rel_o$33 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1];
+  assign \$840  = \$838  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_c_0;
+  assign \$842  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_c_cr0_0;
+  assign \$844  = \$840  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$842 ;
+  assign \$846  = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_c_en_o;
+  assign \$848  = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ;
+  assign \$850  = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \$848 ;
+  assign \$852  = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$850  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  assign \$854  = \fus_cu_rd__rel_o$74 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
+  assign \$856  = \$854  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
+  assign \$858  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_0;
+  assign \$860  = \$856  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$858 ;
+  assign \$862  = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$864  = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
+  assign \$866  = \fus_cu_rd__rel_o$36 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
+  assign \$868  = \$866  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
+  assign \$870  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_1;
+  assign \$872  = \$868  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$870 ;
+  assign \$874  = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$876  = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
+  assign \$878  = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$880  = \$878  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0;
+  assign \$882  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_spr0_2;
+  assign \$884  = \$880  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$882 ;
+  assign \$886  = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$888  = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0;
+  assign \$890  = \fus_cu_rd__rel_o$74 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2];
+  assign \$892  = \$890  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1;
+  assign \$894  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_3;
+  assign \$896  = \$892  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$894 ;
+  assign \$898  = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$900  = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0;
+  assign \$902  = \fus_cu_rd__rel_o$36 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
+  assign \$904  = \$902  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1;
+  assign \$906  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_4;
+  assign \$908  = \$904  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$906 ;
+  assign \$910  = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$912  = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0;
+  assign \$914  = \fus_cu_rd__rel_o$36 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3];
+  assign \$916  = \$914  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_2;
+  assign \$918  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_5;
+  assign \$920  = \$916  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$918 ;
+  assign \$922  = rdpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o;
+  assign \$924  = rp_FAST_fast1_trap0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast3 : 3'h0;
+  assign \$927  = addr_en_FAST_fast1_trap0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_spr0_2;
+  assign \$929  = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$927 ;
+  assign \$931  = addr_en_FAST_fast1_trap0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_5;
+  assign \$933  = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$931 ;
+  assign \$935  = \$929  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$933 ;
+  assign \$926  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$935 ;
+  assign \$938  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_FAST_fast1_trap0_5, rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 };
+  assign \$940  = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5];
+  assign \$942  = \$940  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_SPR_spr1_0;
+  assign \$944  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_SPR_spr1_spr0_0;
+  assign \$946  = \$942  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$944 ;
+  assign \$948  = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_SPR_spr1_en_o;
+  assign \$950  = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_spr1 : 10'h000;
+  assign \$952  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) rp_SPR_spr1_spr0_0;
+  assign \$954  = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o;
+  assign \$956  = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0];
+  assign \$958  = \fus_cu_wr__rel_o$87 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1];
+  assign \$960  = \fus_cu_wr__rel_o$90 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3];
+  assign \$962  = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4];
+  assign \$964  = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5];
+  assign \$966  = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6];
+  assign \$968  = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7];
+  assign \$970  = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8];
+  assign \$972  = \fus_cu_wr__rel_o$107 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9];
+  assign \$974  = \fus_cu_wr__rel_o$107 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9];
+  assign \$976  = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$978  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly;
+  assign \$980  = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$978 ;
+  assign \$986  = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o;
+  assign \$988  = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00;
+  assign \$990  = \fus_o_ok$86  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$7 ;
+  assign \$993  = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o;
+  assign \$997  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$995 ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1860  <= \wr_pick_dly$1860$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1840  <= \wr_pick_dly$1840$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1820  <= \wr_pick_dly$1820$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1796  <= \wr_pick_dly$1796$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1780  <= \wr_pick_dly$1780$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1728  <= \wr_pick_dly$1728$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1712  <= \wr_pick_dly$1712$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1696  <= \wr_pick_dly$1696$next ;
+  always @(posedge coresync_clk)
+    \wr_pick_dly$1680  <= \wr_pick_dly$1680$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1678  <= \wr_pick_dly$1678$next ;
+    \wr_pick_dly$1664  <= \wr_pick_dly$1664$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1659  <= \wr_pick_dly$1659$next ;
+    \wr_pick_dly$1645  <= \wr_pick_dly$1645$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1615  <= \wr_pick_dly$1615$next ;
+    \wr_pick_dly$1601  <= \wr_pick_dly$1601$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1599  <= \wr_pick_dly$1599$next ;
+    \wr_pick_dly$1585  <= \wr_pick_dly$1585$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1583  <= \wr_pick_dly$1583$next ;
+    \wr_pick_dly$1569  <= \wr_pick_dly$1569$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1567  <= \wr_pick_dly$1567$next ;
+    \wr_pick_dly$1553  <= \wr_pick_dly$1553$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1531  <= \wr_pick_dly$1531$next ;
+    \wr_pick_dly$1517  <= \wr_pick_dly$1517$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1515  <= \wr_pick_dly$1515$next ;
+    \wr_pick_dly$1501  <= \wr_pick_dly$1501$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1499  <= \wr_pick_dly$1499$next ;
+    \wr_pick_dly$1485  <= \wr_pick_dly$1485$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1483  <= \wr_pick_dly$1483$next ;
+    \wr_pick_dly$1469  <= \wr_pick_dly$1469$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1449  <= \wr_pick_dly$1449$next ;
+    \wr_pick_dly$1435  <= \wr_pick_dly$1435$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1433  <= \wr_pick_dly$1433$next ;
+    \wr_pick_dly$1419  <= \wr_pick_dly$1419$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1417  <= \wr_pick_dly$1417$next ;
+    \wr_pick_dly$1403  <= \wr_pick_dly$1403$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1370  <= \wr_pick_dly$1370$next ;
+    \wr_pick_dly$1356  <= \wr_pick_dly$1356$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1350  <= \wr_pick_dly$1350$next ;
+    \wr_pick_dly$1336  <= \wr_pick_dly$1336$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1330  <= \wr_pick_dly$1330$next ;
+    \wr_pick_dly$1316  <= \wr_pick_dly$1316$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1310  <= \wr_pick_dly$1310$next ;
+    \wr_pick_dly$1296  <= \wr_pick_dly$1296$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1290  <= \wr_pick_dly$1290$next ;
+    \wr_pick_dly$1276  <= \wr_pick_dly$1276$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1270  <= \wr_pick_dly$1270$next ;
+    \wr_pick_dly$1256  <= \wr_pick_dly$1256$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1242  <= \wr_pick_dly$1242$next ;
+    \wr_pick_dly$1228  <= \wr_pick_dly$1228$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1168  <= \wr_pick_dly$1168$next ;
+    \wr_pick_dly$1154  <= \wr_pick_dly$1154$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1150  <= \wr_pick_dly$1150$next ;
+    \wr_pick_dly$1136  <= \wr_pick_dly$1136$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1131  <= \wr_pick_dly$1131$next ;
+    \wr_pick_dly$1117  <= \wr_pick_dly$1117$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1111  <= \wr_pick_dly$1111$next ;
+    \wr_pick_dly$1097  <= \wr_pick_dly$1097$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1091  <= \wr_pick_dly$1091$next ;
+    \wr_pick_dly$1077  <= \wr_pick_dly$1077$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1069  <= \wr_pick_dly$1069$next ;
+    \wr_pick_dly$1055  <= \wr_pick_dly$1055$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1051  <= \wr_pick_dly$1051$next ;
+    \wr_pick_dly$1037  <= \wr_pick_dly$1037$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1028  <= \wr_pick_dly$1028$next ;
+    \wr_pick_dly$1014  <= \wr_pick_dly$1014$next ;
   always @(posedge coresync_clk)
-    \wr_pick_dly$1009  <= \wr_pick_dly$1009$next ;
+    \wr_pick_dly$995  <= \wr_pick_dly$995$next ;
   always @(posedge coresync_clk)
     wr_pick_dly <= \wr_pick_dly$next ;
   always @(posedge coresync_clk)
@@ -46544,7 +46544,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .dest1__data_i(fast_dest1__data_i),
     .dest1__wen(fast_dest1__wen),
     .issue__addr(issue__addr),
-    .\issue__addr$1 (\issue__addr$12 ),
+    .\issue__addr$1 (\issue__addr$5 ),
     .issue__data_i(issue__data_i),
     .issue__data_o(issue__data_o),
     .issue__ren(issue__ren),
@@ -46557,129 +46557,129 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
     .cr_a_ok(fus_cr_a_ok),
-    .\cr_a_ok$111 (\fus_cr_a_ok$123 ),
-    .\cr_a_ok$112 (\fus_cr_a_ok$124 ),
-    .\cr_a_ok$113 (\fus_cr_a_ok$125 ),
-    .\cr_a_ok$114 (\fus_cr_a_ok$126 ),
-    .\cr_a_ok$115 (\fus_cr_a_ok$127 ),
+    .\cr_a_ok$111 (\fus_cr_a_ok$116 ),
+    .\cr_a_ok$112 (\fus_cr_a_ok$117 ),
+    .\cr_a_ok$113 (\fus_cr_a_ok$118 ),
+    .\cr_a_ok$114 (\fus_cr_a_ok$119 ),
+    .\cr_a_ok$115 (\fus_cr_a_ok$120 ),
     .cu_ad__go_i(cu_ad__go_i),
     .cu_ad__rel_o(cu_ad__rel_o),
     .cu_busy_o(fus_cu_busy_o),
-    .\cu_busy_o$11 (\fus_cu_busy_o$23 ),
-    .\cu_busy_o$14 (\fus_cu_busy_o$26 ),
-    .\cu_busy_o$17 (\fus_cu_busy_o$29 ),
-    .\cu_busy_o$2 (\fus_cu_busy_o$14 ),
-    .\cu_busy_o$20 (\fus_cu_busy_o$32 ),
-    .\cu_busy_o$23 (\fus_cu_busy_o$35 ),
-    .\cu_busy_o$26 (\fus_cu_busy_o$38 ),
-    .\cu_busy_o$5 (\fus_cu_busy_o$17 ),
-    .\cu_busy_o$8 (\fus_cu_busy_o$20 ),
+    .\cu_busy_o$11 (\fus_cu_busy_o$16 ),
+    .\cu_busy_o$14 (\fus_cu_busy_o$19 ),
+    .\cu_busy_o$17 (\fus_cu_busy_o$22 ),
+    .\cu_busy_o$2 (\fus_cu_busy_o$7 ),
+    .\cu_busy_o$20 (\fus_cu_busy_o$25 ),
+    .\cu_busy_o$23 (\fus_cu_busy_o$28 ),
+    .\cu_busy_o$26 (\fus_cu_busy_o$31 ),
+    .\cu_busy_o$5 (\fus_cu_busy_o$10 ),
+    .\cu_busy_o$8 (\fus_cu_busy_o$13 ),
     .cu_issue_i(fus_cu_issue_i),
-    .\cu_issue_i$1 (\fus_cu_issue_i$13 ),
-    .\cu_issue_i$10 (\fus_cu_issue_i$22 ),
-    .\cu_issue_i$13 (\fus_cu_issue_i$25 ),
-    .\cu_issue_i$16 (\fus_cu_issue_i$28 ),
-    .\cu_issue_i$19 (\fus_cu_issue_i$31 ),
-    .\cu_issue_i$22 (\fus_cu_issue_i$34 ),
-    .\cu_issue_i$25 (\fus_cu_issue_i$37 ),
-    .\cu_issue_i$4 (\fus_cu_issue_i$16 ),
-    .\cu_issue_i$7 (\fus_cu_issue_i$19 ),
+    .\cu_issue_i$1 (\fus_cu_issue_i$6 ),
+    .\cu_issue_i$10 (\fus_cu_issue_i$15 ),
+    .\cu_issue_i$13 (\fus_cu_issue_i$18 ),
+    .\cu_issue_i$16 (\fus_cu_issue_i$21 ),
+    .\cu_issue_i$19 (\fus_cu_issue_i$24 ),
+    .\cu_issue_i$22 (\fus_cu_issue_i$27 ),
+    .\cu_issue_i$25 (\fus_cu_issue_i$30 ),
+    .\cu_issue_i$4 (\fus_cu_issue_i$9 ),
+    .\cu_issue_i$7 (\fus_cu_issue_i$12 ),
     .cu_rd__go_i(fus_cu_rd__go_i),
-    .\cu_rd__go_i$29 (\fus_cu_rd__go_i$41 ),
-    .\cu_rd__go_i$32 (\fus_cu_rd__go_i$44 ),
-    .\cu_rd__go_i$35 (\fus_cu_rd__go_i$47 ),
-    .\cu_rd__go_i$38 (\fus_cu_rd__go_i$50 ),
-    .\cu_rd__go_i$41 (\fus_cu_rd__go_i$53 ),
-    .\cu_rd__go_i$44 (\fus_cu_rd__go_i$56 ),
-    .\cu_rd__go_i$47 (\fus_cu_rd__go_i$59 ),
-    .\cu_rd__go_i$54 (\fus_cu_rd__go_i$66 ),
-    .\cu_rd__go_i$70 (\fus_cu_rd__go_i$82 ),
+    .\cu_rd__go_i$29 (\fus_cu_rd__go_i$34 ),
+    .\cu_rd__go_i$32 (\fus_cu_rd__go_i$37 ),
+    .\cu_rd__go_i$35 (\fus_cu_rd__go_i$40 ),
+    .\cu_rd__go_i$38 (\fus_cu_rd__go_i$43 ),
+    .\cu_rd__go_i$41 (\fus_cu_rd__go_i$46 ),
+    .\cu_rd__go_i$44 (\fus_cu_rd__go_i$49 ),
+    .\cu_rd__go_i$47 (\fus_cu_rd__go_i$52 ),
+    .\cu_rd__go_i$54 (\fus_cu_rd__go_i$59 ),
+    .\cu_rd__go_i$70 (\fus_cu_rd__go_i$75 ),
     .cu_rd__rel_o(fus_cu_rd__rel_o),
-    .\cu_rd__rel_o$28 (\fus_cu_rd__rel_o$40 ),
-    .\cu_rd__rel_o$31 (\fus_cu_rd__rel_o$43 ),
-    .\cu_rd__rel_o$34 (\fus_cu_rd__rel_o$46 ),
-    .\cu_rd__rel_o$37 (\fus_cu_rd__rel_o$49 ),
-    .\cu_rd__rel_o$40 (\fus_cu_rd__rel_o$52 ),
-    .\cu_rd__rel_o$43 (\fus_cu_rd__rel_o$55 ),
-    .\cu_rd__rel_o$46 (\fus_cu_rd__rel_o$58 ),
-    .\cu_rd__rel_o$53 (\fus_cu_rd__rel_o$65 ),
-    .\cu_rd__rel_o$69 (\fus_cu_rd__rel_o$81 ),
+    .\cu_rd__rel_o$28 (\fus_cu_rd__rel_o$33 ),
+    .\cu_rd__rel_o$31 (\fus_cu_rd__rel_o$36 ),
+    .\cu_rd__rel_o$34 (\fus_cu_rd__rel_o$39 ),
+    .\cu_rd__rel_o$37 (\fus_cu_rd__rel_o$42 ),
+    .\cu_rd__rel_o$40 (\fus_cu_rd__rel_o$45 ),
+    .\cu_rd__rel_o$43 (\fus_cu_rd__rel_o$48 ),
+    .\cu_rd__rel_o$46 (\fus_cu_rd__rel_o$51 ),
+    .\cu_rd__rel_o$53 (\fus_cu_rd__rel_o$58 ),
+    .\cu_rd__rel_o$69 (\fus_cu_rd__rel_o$74 ),
     .cu_rdmaskn_i(fus_cu_rdmaskn_i),
-    .\cu_rdmaskn_i$12 (\fus_cu_rdmaskn_i$24 ),
-    .\cu_rdmaskn_i$15 (\fus_cu_rdmaskn_i$27 ),
-    .\cu_rdmaskn_i$18 (\fus_cu_rdmaskn_i$30 ),
-    .\cu_rdmaskn_i$21 (\fus_cu_rdmaskn_i$33 ),
-    .\cu_rdmaskn_i$24 (\fus_cu_rdmaskn_i$36 ),
-    .\cu_rdmaskn_i$27 (\fus_cu_rdmaskn_i$39 ),
-    .\cu_rdmaskn_i$3 (\fus_cu_rdmaskn_i$15 ),
-    .\cu_rdmaskn_i$6 (\fus_cu_rdmaskn_i$18 ),
-    .\cu_rdmaskn_i$9 (\fus_cu_rdmaskn_i$21 ),
+    .\cu_rdmaskn_i$12 (\fus_cu_rdmaskn_i$17 ),
+    .\cu_rdmaskn_i$15 (\fus_cu_rdmaskn_i$20 ),
+    .\cu_rdmaskn_i$18 (\fus_cu_rdmaskn_i$23 ),
+    .\cu_rdmaskn_i$21 (\fus_cu_rdmaskn_i$26 ),
+    .\cu_rdmaskn_i$24 (\fus_cu_rdmaskn_i$29 ),
+    .\cu_rdmaskn_i$27 (\fus_cu_rdmaskn_i$32 ),
+    .\cu_rdmaskn_i$3 (\fus_cu_rdmaskn_i$8 ),
+    .\cu_rdmaskn_i$6 (\fus_cu_rdmaskn_i$11 ),
+    .\cu_rdmaskn_i$9 (\fus_cu_rdmaskn_i$14 ),
     .cu_st__go_i(cu_st__go_i),
     .cu_st__rel_o(cu_st__rel_o),
     .cu_wr__go_i(fus_cu_wr__go_i),
-    .\cu_wr__go_i$101 (\fus_cu_wr__go_i$113 ),
-    .\cu_wr__go_i$103 (\fus_cu_wr__go_i$115 ),
-    .\cu_wr__go_i$138 (\fus_cu_wr__go_i$150 ),
-    .\cu_wr__go_i$83 (\fus_cu_wr__go_i$95 ),
-    .\cu_wr__go_i$86 (\fus_cu_wr__go_i$98 ),
-    .\cu_wr__go_i$89 (\fus_cu_wr__go_i$101 ),
-    .\cu_wr__go_i$92 (\fus_cu_wr__go_i$104 ),
-    .\cu_wr__go_i$95 (\fus_cu_wr__go_i$107 ),
-    .\cu_wr__go_i$98 (\fus_cu_wr__go_i$110 ),
+    .\cu_wr__go_i$101 (\fus_cu_wr__go_i$106 ),
+    .\cu_wr__go_i$103 (\fus_cu_wr__go_i$108 ),
+    .\cu_wr__go_i$138 (\fus_cu_wr__go_i$143 ),
+    .\cu_wr__go_i$83 (\fus_cu_wr__go_i$88 ),
+    .\cu_wr__go_i$86 (\fus_cu_wr__go_i$91 ),
+    .\cu_wr__go_i$89 (\fus_cu_wr__go_i$94 ),
+    .\cu_wr__go_i$92 (\fus_cu_wr__go_i$97 ),
+    .\cu_wr__go_i$95 (\fus_cu_wr__go_i$100 ),
+    .\cu_wr__go_i$98 (\fus_cu_wr__go_i$103 ),
     .cu_wr__rel_o(fus_cu_wr__rel_o),
-    .\cu_wr__rel_o$100 (\fus_cu_wr__rel_o$112 ),
-    .\cu_wr__rel_o$102 (\fus_cu_wr__rel_o$114 ),
-    .\cu_wr__rel_o$137 (\fus_cu_wr__rel_o$149 ),
-    .\cu_wr__rel_o$82 (\fus_cu_wr__rel_o$94 ),
-    .\cu_wr__rel_o$85 (\fus_cu_wr__rel_o$97 ),
-    .\cu_wr__rel_o$88 (\fus_cu_wr__rel_o$100 ),
-    .\cu_wr__rel_o$91 (\fus_cu_wr__rel_o$103 ),
-    .\cu_wr__rel_o$94 (\fus_cu_wr__rel_o$106 ),
-    .\cu_wr__rel_o$97 (\fus_cu_wr__rel_o$109 ),
+    .\cu_wr__rel_o$100 (\fus_cu_wr__rel_o$105 ),
+    .\cu_wr__rel_o$102 (\fus_cu_wr__rel_o$107 ),
+    .\cu_wr__rel_o$137 (\fus_cu_wr__rel_o$142 ),
+    .\cu_wr__rel_o$82 (\fus_cu_wr__rel_o$87 ),
+    .\cu_wr__rel_o$85 (\fus_cu_wr__rel_o$90 ),
+    .\cu_wr__rel_o$88 (\fus_cu_wr__rel_o$93 ),
+    .\cu_wr__rel_o$91 (\fus_cu_wr__rel_o$96 ),
+    .\cu_wr__rel_o$94 (\fus_cu_wr__rel_o$99 ),
+    .\cu_wr__rel_o$97 (\fus_cu_wr__rel_o$102 ),
     .dest1_o(fus_dest1_o),
-    .\dest1_o$104 (\fus_dest1_o$116 ),
-    .\dest1_o$105 (\fus_dest1_o$117 ),
-    .\dest1_o$106 (\fus_dest1_o$118 ),
-    .\dest1_o$107 (\fus_dest1_o$119 ),
-    .\dest1_o$108 (\fus_dest1_o$120 ),
-    .\dest1_o$109 (\fus_dest1_o$121 ),
-    .\dest1_o$110 (\fus_dest1_o$122 ),
-    .\dest1_o$142 (\fus_dest1_o$154 ),
+    .\dest1_o$104 (\fus_dest1_o$109 ),
+    .\dest1_o$105 (\fus_dest1_o$110 ),
+    .\dest1_o$106 (\fus_dest1_o$111 ),
+    .\dest1_o$107 (\fus_dest1_o$112 ),
+    .\dest1_o$108 (\fus_dest1_o$113 ),
+    .\dest1_o$109 (\fus_dest1_o$114 ),
+    .\dest1_o$110 (\fus_dest1_o$115 ),
+    .\dest1_o$142 (\fus_dest1_o$147 ),
     .dest2_o(fus_dest2_o),
-    .\dest2_o$116 (\fus_dest2_o$128 ),
-    .\dest2_o$117 (\fus_dest2_o$129 ),
-    .\dest2_o$118 (\fus_dest2_o$130 ),
-    .\dest2_o$119 (\fus_dest2_o$131 ),
-    .\dest2_o$120 (\fus_dest2_o$132 ),
-    .\dest2_o$143 (\fus_dest2_o$155 ),
-    .\dest2_o$145 (\fus_dest2_o$157 ),
-    .\dest2_o$152 (\fus_dest2_o$164 ),
+    .\dest2_o$116 (\fus_dest2_o$121 ),
+    .\dest2_o$117 (\fus_dest2_o$122 ),
+    .\dest2_o$118 (\fus_dest2_o$123 ),
+    .\dest2_o$119 (\fus_dest2_o$124 ),
+    .\dest2_o$120 (\fus_dest2_o$125 ),
+    .\dest2_o$143 (\fus_dest2_o$148 ),
+    .\dest2_o$145 (\fus_dest2_o$150 ),
+    .\dest2_o$152 (\fus_dest2_o$157 ),
     .dest3_o(fus_dest3_o),
-    .\dest3_o$123 (\fus_dest3_o$135 ),
-    .\dest3_o$124 (\fus_dest3_o$136 ),
-    .\dest3_o$128 (\fus_dest3_o$140 ),
-    .\dest3_o$129 (\fus_dest3_o$141 ),
-    .\dest3_o$144 (\fus_dest3_o$156 ),
-    .\dest3_o$146 (\fus_dest3_o$158 ),
-    .\dest3_o$149 (\fus_dest3_o$161 ),
+    .\dest3_o$123 (\fus_dest3_o$128 ),
+    .\dest3_o$124 (\fus_dest3_o$129 ),
+    .\dest3_o$128 (\fus_dest3_o$133 ),
+    .\dest3_o$129 (\fus_dest3_o$134 ),
+    .\dest3_o$144 (\fus_dest3_o$149 ),
+    .\dest3_o$146 (\fus_dest3_o$151 ),
+    .\dest3_o$149 (\fus_dest3_o$154 ),
     .dest4_o(fus_dest4_o),
-    .\dest4_o$134 (\fus_dest4_o$146 ),
-    .\dest4_o$135 (\fus_dest4_o$147 ),
-    .\dest4_o$136 (\fus_dest4_o$148 ),
-    .\dest4_o$147 (\fus_dest4_o$159 ),
+    .\dest4_o$134 (\fus_dest4_o$139 ),
+    .\dest4_o$135 (\fus_dest4_o$140 ),
+    .\dest4_o$136 (\fus_dest4_o$141 ),
+    .\dest4_o$147 (\fus_dest4_o$152 ),
     .dest5_o(fus_dest5_o),
-    .\dest5_o$133 (\fus_dest5_o$145 ),
-    .\dest5_o$150 (\fus_dest5_o$162 ),
+    .\dest5_o$133 (\fus_dest5_o$138 ),
+    .\dest5_o$150 (\fus_dest5_o$155 ),
     .dest6_o(fus_dest6_o),
-    .\dest6_o$151 (\fus_dest6_o$163 ),
+    .\dest6_o$151 (\fus_dest6_o$156 ),
     .dest7_o(fus_dest7_o),
     .ea(fus_ea),
-    .\exc_o_$signal (\exc_o_$signal ),
+    .exc_o_happened(exc_o_happened),
     .fast1_ok(fus_fast1_ok),
-    .\fast1_ok$139 (\fus_fast1_ok$151 ),
-    .\fast1_ok$140 (\fus_fast1_ok$152 ),
+    .\fast1_ok$139 (\fus_fast1_ok$144 ),
+    .\fast1_ok$140 (\fus_fast1_ok$145 ),
     .fast2_ok(fus_fast2_ok),
-    .\fast2_ok$141 (\fus_fast2_ok$153 ),
+    .\fast2_ok$141 (\fus_fast2_ok$146 ),
     .fast3_ok(fus_fast3_ok),
     .full_cr_ok(fus_full_cr_ok),
     .ldst_port0_addr_i(fus_ldst_port0_addr_i),
@@ -46687,14 +46687,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o),
     .ldst_port0_busy_o(fus_ldst_port0_busy_o),
     .ldst_port0_data_len(fus_ldst_port0_data_len),
-    .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ),
-    .\ldst_port0_exc_$signal$153 (\fus_ldst_port0_exc_$signal$165 ),
-    .\ldst_port0_exc_$signal$154 (\fus_ldst_port0_exc_$signal$166 ),
-    .\ldst_port0_exc_$signal$155 (\fus_ldst_port0_exc_$signal$167 ),
-    .\ldst_port0_exc_$signal$156 (\fus_ldst_port0_exc_$signal$168 ),
-    .\ldst_port0_exc_$signal$157 (\fus_ldst_port0_exc_$signal$169 ),
-    .\ldst_port0_exc_$signal$158 (\fus_ldst_port0_exc_$signal$170 ),
-    .\ldst_port0_exc_$signal$159 (\fus_ldst_port0_exc_$signal$171 ),
+    .ldst_port0_exc_alignment(fus_ldst_port0_exc_alignment),
+    .ldst_port0_exc_badtree(fus_ldst_port0_exc_badtree),
+    .ldst_port0_exc_happened(fus_ldst_port0_exc_happened),
+    .ldst_port0_exc_instr_fault(fus_ldst_port0_exc_instr_fault),
+    .ldst_port0_exc_invalid(fus_ldst_port0_exc_invalid),
+    .ldst_port0_exc_perm_error(fus_ldst_port0_exc_perm_error),
+    .ldst_port0_exc_rc_error(fus_ldst_port0_exc_rc_error),
+    .ldst_port0_exc_segment_fault(fus_ldst_port0_exc_segment_fault),
     .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i),
     .ldst_port0_is_st_i(fus_ldst_port0_is_st_i),
     .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o),
@@ -46704,16 +46704,16 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok),
     .msr_ok(fus_msr_ok),
     .nia_ok(fus_nia_ok),
-    .\nia_ok$148 (\fus_nia_ok$160 ),
+    .\nia_ok$148 (\fus_nia_ok$153 ),
     .o(fus_o),
     .o_ok(fus_o_ok),
-    .\o_ok$81 (\fus_o_ok$93 ),
-    .\o_ok$84 (\fus_o_ok$96 ),
-    .\o_ok$87 (\fus_o_ok$99 ),
-    .\o_ok$90 (\fus_o_ok$102 ),
-    .\o_ok$93 (\fus_o_ok$105 ),
-    .\o_ok$96 (\fus_o_ok$108 ),
-    .\o_ok$99 (\fus_o_ok$111 ),
+    .\o_ok$81 (\fus_o_ok$86 ),
+    .\o_ok$84 (\fus_o_ok$89 ),
+    .\o_ok$87 (\fus_o_ok$92 ),
+    .\o_ok$90 (\fus_o_ok$95 ),
+    .\o_ok$93 (\fus_o_ok$98 ),
+    .\o_ok$96 (\fus_o_ok$101 ),
+    .\o_ok$99 (\fus_o_ok$104 ),
     .oper_i_alu_alu0__SV_Ptype(fus_oper_i_alu_alu0__SV_Ptype),
     .oper_i_alu_alu0__data_len(fus_oper_i_alu_alu0__data_len),
     .oper_i_alu_alu0__fn_unit(fus_oper_i_alu_alu0__fn_unit),
@@ -46881,58 +46881,58 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .oper_i_ldst_ldst0__zero_a(fus_oper_i_ldst_ldst0__zero_a),
     .spr1_ok(fus_spr1_ok),
     .src1_i(fus_src1_i),
-    .\src1_i$50 (\fus_src1_i$62 ),
-    .\src1_i$51 (\fus_src1_i$63 ),
-    .\src1_i$52 (\fus_src1_i$64 ),
-    .\src1_i$55 (\fus_src1_i$67 ),
-    .\src1_i$56 (\fus_src1_i$68 ),
-    .\src1_i$57 (\fus_src1_i$69 ),
-    .\src1_i$58 (\fus_src1_i$70 ),
-    .\src1_i$59 (\fus_src1_i$71 ),
-    .\src1_i$74 (\fus_src1_i$86 ),
+    .\src1_i$50 (\fus_src1_i$55 ),
+    .\src1_i$51 (\fus_src1_i$56 ),
+    .\src1_i$52 (\fus_src1_i$57 ),
+    .\src1_i$55 (\fus_src1_i$60 ),
+    .\src1_i$56 (\fus_src1_i$61 ),
+    .\src1_i$57 (\fus_src1_i$62 ),
+    .\src1_i$58 (\fus_src1_i$63 ),
+    .\src1_i$59 (\fus_src1_i$64 ),
+    .\src1_i$74 (\fus_src1_i$79 ),
     .src2_i(fus_src2_i),
-    .\src2_i$30 (\fus_src2_i$42 ),
-    .\src2_i$33 (\fus_src2_i$45 ),
-    .\src2_i$36 (\fus_src2_i$48 ),
-    .\src2_i$39 (\fus_src2_i$51 ),
-    .\src2_i$42 (\fus_src2_i$54 ),
-    .\src2_i$45 (\fus_src2_i$57 ),
-    .\src2_i$48 (\fus_src2_i$60 ),
-    .\src2_i$77 (\fus_src2_i$89 ),
-    .\src2_i$80 (\fus_src2_i$92 ),
+    .\src2_i$30 (\fus_src2_i$35 ),
+    .\src2_i$33 (\fus_src2_i$38 ),
+    .\src2_i$36 (\fus_src2_i$41 ),
+    .\src2_i$39 (\fus_src2_i$44 ),
+    .\src2_i$42 (\fus_src2_i$47 ),
+    .\src2_i$45 (\fus_src2_i$50 ),
+    .\src2_i$48 (\fus_src2_i$53 ),
+    .\src2_i$77 (\fus_src2_i$82 ),
+    .\src2_i$80 (\fus_src2_i$85 ),
     .src3_i(fus_src3_i),
-    .\src3_i$49 (\fus_src3_i$61 ),
-    .\src3_i$60 (\fus_src3_i$72 ),
-    .\src3_i$61 (\fus_src3_i$73 ),
-    .\src3_i$62 (\fus_src3_i$74 ),
-    .\src3_i$63 (\fus_src3_i$75 ),
-    .\src3_i$67 (\fus_src3_i$79 ),
-    .\src3_i$71 (\fus_src3_i$83 ),
-    .\src3_i$75 (\fus_src3_i$87 ),
-    .\src3_i$76 (\fus_src3_i$88 ),
+    .\src3_i$49 (\fus_src3_i$54 ),
+    .\src3_i$60 (\fus_src3_i$65 ),
+    .\src3_i$61 (\fus_src3_i$66 ),
+    .\src3_i$62 (\fus_src3_i$67 ),
+    .\src3_i$63 (\fus_src3_i$68 ),
+    .\src3_i$67 (\fus_src3_i$72 ),
+    .\src3_i$71 (\fus_src3_i$76 ),
+    .\src3_i$75 (\fus_src3_i$80 ),
+    .\src3_i$76 (\fus_src3_i$81 ),
     .src4_i(fus_src4_i),
-    .\src4_i$64 (\fus_src4_i$76 ),
-    .\src4_i$65 (\fus_src4_i$77 ),
-    .\src4_i$68 (\fus_src4_i$80 ),
-    .\src4_i$78 (\fus_src4_i$90 ),
+    .\src4_i$64 (\fus_src4_i$69 ),
+    .\src4_i$65 (\fus_src4_i$70 ),
+    .\src4_i$68 (\fus_src4_i$73 ),
+    .\src4_i$78 (\fus_src4_i$83 ),
     .src5_i(fus_src5_i),
-    .\src5_i$66 (\fus_src5_i$78 ),
-    .\src5_i$72 (\fus_src5_i$84 ),
-    .\src5_i$79 (\fus_src5_i$91 ),
+    .\src5_i$66 (\fus_src5_i$71 ),
+    .\src5_i$72 (\fus_src5_i$77 ),
+    .\src5_i$79 (\fus_src5_i$84 ),
     .src6_i(fus_src6_i),
-    .\src6_i$73 (\fus_src6_i$85 ),
+    .\src6_i$73 (\fus_src6_i$78 ),
     .svstate_ok(fus_svstate_ok),
     .xer_ca_ok(fus_xer_ca_ok),
-    .\xer_ca_ok$121 (\fus_xer_ca_ok$133 ),
-    .\xer_ca_ok$122 (\fus_xer_ca_ok$134 ),
+    .\xer_ca_ok$121 (\fus_xer_ca_ok$126 ),
+    .\xer_ca_ok$122 (\fus_xer_ca_ok$127 ),
     .xer_ov_ok(fus_xer_ov_ok),
-    .\xer_ov_ok$125 (\fus_xer_ov_ok$137 ),
-    .\xer_ov_ok$126 (\fus_xer_ov_ok$138 ),
-    .\xer_ov_ok$127 (\fus_xer_ov_ok$139 ),
+    .\xer_ov_ok$125 (\fus_xer_ov_ok$130 ),
+    .\xer_ov_ok$126 (\fus_xer_ov_ok$131 ),
+    .\xer_ov_ok$127 (\fus_xer_ov_ok$132 ),
     .xer_so_ok(fus_xer_so_ok),
-    .\xer_so_ok$130 (\fus_xer_so_ok$142 ),
-    .\xer_so_ok$131 (\fus_xer_so_ok$143 ),
-    .\xer_so_ok$132 (\fus_xer_so_ok$144 )
+    .\xer_so_ok$130 (\fus_xer_so_ok$135 ),
+    .\xer_so_ok$131 (\fus_xer_so_ok$136 ),
+    .\xer_so_ok$132 (\fus_xer_so_ok$137 )
   );
   \int  \int  (
     .coresync_clk(coresync_clk),
@@ -46964,14 +46964,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o),
     .ldst_port0_busy_o(fus_ldst_port0_busy_o),
     .ldst_port0_data_len(fus_ldst_port0_data_len),
-    .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ),
-    .\ldst_port0_exc_$signal$1 (\fus_ldst_port0_exc_$signal$165 ),
-    .\ldst_port0_exc_$signal$2 (\fus_ldst_port0_exc_$signal$166 ),
-    .\ldst_port0_exc_$signal$3 (\fus_ldst_port0_exc_$signal$167 ),
-    .\ldst_port0_exc_$signal$4 (\fus_ldst_port0_exc_$signal$168 ),
-    .\ldst_port0_exc_$signal$5 (\fus_ldst_port0_exc_$signal$169 ),
-    .\ldst_port0_exc_$signal$6 (\fus_ldst_port0_exc_$signal$170 ),
-    .\ldst_port0_exc_$signal$7 (\fus_ldst_port0_exc_$signal$171 ),
+    .ldst_port0_exc_alignment(fus_ldst_port0_exc_alignment),
+    .ldst_port0_exc_badtree(fus_ldst_port0_exc_badtree),
+    .ldst_port0_exc_happened(fus_ldst_port0_exc_happened),
+    .ldst_port0_exc_instr_fault(fus_ldst_port0_exc_instr_fault),
+    .ldst_port0_exc_invalid(fus_ldst_port0_exc_invalid),
+    .ldst_port0_exc_perm_error(fus_ldst_port0_exc_perm_error),
+    .ldst_port0_exc_rc_error(fus_ldst_port0_exc_rc_error),
+    .ldst_port0_exc_segment_fault(fus_ldst_port0_exc_segment_fault),
     .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i),
     .ldst_port0_is_st_i(fus_ldst_port0_is_st_i),
     .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o),
@@ -47035,7 +47035,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
     .spr1__addr(spr_spr1__addr),
-    .\spr1__addr$1 (\spr_spr1__addr$179 ),
+    .\spr1__addr$1 (\spr_spr1__addr$165 ),
     .spr1__data_i(spr_spr1__data_i),
     .spr1__data_o(spr_spr1__data_o),
     .spr1__ren(spr_spr1__ren),
@@ -47047,19 +47047,19 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
     .data_i(data_i),
-    .\data_i$2 (\data_i$11 ),
+    .\data_i$2 (\data_i$4 ),
     .\data_i$3 (state_data_i),
-    .\data_i$4 (\state_data_i$176 ),
-    .\data_i$6 (\state_data_i$177 ),
+    .\data_i$4 (\state_data_i$162 ),
+    .\data_i$6 (\state_data_i$163 ),
     .msr__data_o(msr__data_o),
     .msr__ren(msr__ren),
     .state_nia_wen(state_nia_wen),
     .sv__data_o(sv__data_o),
     .sv__ren(sv__ren),
     .wen(wen),
-    .\wen$1 (\wen$10 ),
+    .\wen$1 (\wen$3 ),
     .\wen$5 (state_wen),
-    .\wen$7 (\state_wen$178 )
+    .\wen$7 (\state_wen$164 )
   );
   wrpick_CR_cr_a wrpick_CR_cr_a (
     .en_o(wrpick_CR_cr_a_en_o),
@@ -47120,8 +47120,8 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
     .data_i(xer_data_i),
-    .\data_i$1 (\xer_data_i$172 ),
-    .\data_i$3 (\xer_data_i$174 ),
+    .\data_i$1 (\xer_data_i$158 ),
+    .\data_i$3 (\xer_data_i$160 ),
     .full_rd__data_o(full_rd__data_o),
     .full_rd__ren(full_rd__ren),
     .src1__data_o(xer_src1__data_o),
@@ -47131,8 +47131,8 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     .src3__data_o(xer_src3__data_o),
     .src3__ren(xer_src3__ren),
     .wen(xer_wen),
-    .\wen$2 (\xer_wen$173 ),
-    .\wen$4 (\xer_wen$175 )
+    .\wen$2 (\xer_wen$159 ),
+    .\wen$4 (\xer_wen$161 )
   );
   always @* begin
     if (\initial ) begin end
@@ -47196,7 +47196,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$19  = 1'h0;
+    \fus_cu_issue_i$12  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -47219,14 +47219,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[3])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$19  = issue_i;
+                      \fus_cu_issue_i$12  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$21  = 5'h00;
+    \fus_cu_rdmaskn_i$14  = 5'h00;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -47249,7 +47249,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[3])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$21  = \$258 ;
+                      \fus_cu_rdmaskn_i$14  = \$244 ;
                 endcase
           endcase
     endcase
@@ -47829,7 +47829,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$22  = 1'h0;
+    \fus_cu_issue_i$15  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -47852,14 +47852,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[4])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$22  = issue_i;
+                      \fus_cu_issue_i$15  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$24  = 3'h0;
+    \fus_cu_rdmaskn_i$17  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -47882,7 +47882,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[4])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$24  = \$260 ;
+                      \fus_cu_rdmaskn_i$17  = \$246 ;
                 endcase
           endcase
     endcase
@@ -48129,7 +48129,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$25  = 1'h0;
+    \fus_cu_issue_i$18  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -48152,14 +48152,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[5])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$25  = issue_i;
+                      \fus_cu_issue_i$18  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$27  = 6'h00;
+    \fus_cu_rdmaskn_i$20  = 6'h00;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -48182,7 +48182,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[5])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$27  = \$274 ;
+                      \fus_cu_rdmaskn_i$20  = \$260 ;
                 endcase
           endcase
     endcase
@@ -48762,7 +48762,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$28  = 1'h0;
+    \fus_cu_issue_i$21  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -48785,14 +48785,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[6])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$28  = issue_i;
+                      \fus_cu_issue_i$21  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$30  = 3'h0;
+    \fus_cu_rdmaskn_i$23  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -48815,7 +48815,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[6])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$30  = \$304 ;
+                      \fus_cu_rdmaskn_i$23  = \$290 ;
                 endcase
           endcase
     endcase
@@ -49215,7 +49215,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$31  = 1'h0;
+    \fus_cu_issue_i$24  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -49238,14 +49238,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[7])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$31  = issue_i;
+                      \fus_cu_issue_i$24  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$33  = 3'h0;
+    \fus_cu_rdmaskn_i$26  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -49268,7 +49268,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[7])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$33  = \$318 ;
+                      \fus_cu_rdmaskn_i$26  = \$304 ;
                 endcase
           endcase
     endcase
@@ -49818,7 +49818,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$34  = 1'h0;
+    \fus_cu_issue_i$27  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -49841,14 +49841,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[8])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$34  = issue_i;
+                      \fus_cu_issue_i$27  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$36  = 5'h00;
+    \fus_cu_rdmaskn_i$29  = 5'h00;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -49871,7 +49871,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[8])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$36  = \$332 ;
+                      \fus_cu_rdmaskn_i$29  = \$318 ;
                 endcase
           endcase
     endcase
@@ -50421,7 +50421,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$37  = 1'h0;
+    \fus_cu_issue_i$30  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -50444,14 +50444,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[9])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$37  = issue_i;
+                      \fus_cu_issue_i$30  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$39  = 3'h0;
+    \fus_cu_rdmaskn_i$32  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -50474,7 +50474,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[9])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$39  = \$354 ;
+                      \fus_cu_rdmaskn_i$32  = \$340 ;
                 endcase
           endcase
     endcase
@@ -50509,12 +50509,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$42  = 64'h0000000000000000;
+    \fus_src2_i$35  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_cr0_1)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$42  = int_src1__data_o;
+          \fus_src2_i$35  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50528,12 +50528,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$45  = 64'h0000000000000000;
+    \fus_src2_i$38  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_trap0_2)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$45  = int_src1__data_o;
+          \fus_src2_i$38  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50547,12 +50547,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$48  = 64'h0000000000000000;
+    \fus_src2_i$41  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_logical0_3)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$48  = int_src1__data_o;
+          \fus_src2_i$41  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50566,12 +50566,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$51  = 64'h0000000000000000;
+    \fus_src2_i$44  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_div0_4)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$51  = int_src1__data_o;
+          \fus_src2_i$44  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50585,12 +50585,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$54  = 64'h0000000000000000;
+    \fus_src2_i$47  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_mul0_5)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$54  = int_src1__data_o;
+          \fus_src2_i$47  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50604,12 +50604,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$57  = 64'h0000000000000000;
+    \fus_src2_i$50  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_shiftrot0_6)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$57  = int_src1__data_o;
+          \fus_src2_i$50  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50623,12 +50623,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$60  = 64'h0000000000000000;
+    \fus_src2_i$53  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_ldst0_7)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$60  = int_src1__data_o;
+          \fus_src2_i$53  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50661,12 +50661,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$61  = 64'h0000000000000000;
+    \fus_src3_i$54  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_ldst0_9)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$61  = int_src1__data_o;
+          \fus_src3_i$54  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50699,12 +50699,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$62  = 64'h0000000000000000;
+    \fus_src1_i$55  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_cr0_11)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$62  = int_src1__data_o;
+          \fus_src1_i$55  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50718,12 +50718,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$63  = 64'h0000000000000000;
+    \fus_src1_i$56  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_trap0_12)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$63  = int_src1__data_o;
+          \fus_src1_i$56  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50737,12 +50737,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$64  = 64'h0000000000000000;
+    \fus_src1_i$57  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_logical0_13)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$64  = int_src1__data_o;
+          \fus_src1_i$57  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50756,12 +50756,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$67  = 64'h0000000000000000;
+    \fus_src1_i$60  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_spr0_14)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$67  = int_src1__data_o;
+          \fus_src1_i$60  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50775,12 +50775,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$68  = 64'h0000000000000000;
+    \fus_src1_i$61  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_div0_15)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$68  = int_src1__data_o;
+          \fus_src1_i$61  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50794,12 +50794,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$69  = 64'h0000000000000000;
+    \fus_src1_i$62  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_mul0_16)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$69  = int_src1__data_o;
+          \fus_src1_i$62  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50813,12 +50813,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$70  = 64'h0000000000000000;
+    \fus_src1_i$63  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_shiftrot0_17)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$70  = int_src1__data_o;
+          \fus_src1_i$63  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50832,12 +50832,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$71  = 64'h0000000000000000;
+    \fus_src1_i$64  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_INT_rabc_ldst0_18)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$71  = int_src1__data_o;
+          \fus_src1_i$64  = int_src1__data_o;
     endcase
   end
   always @* begin
@@ -50851,12 +50851,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$72  = 1'h0;
+    \fus_src3_i$65  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_so_alu0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$72  = xer_src1__data_o[0];
+          \fus_src3_i$65  = xer_src1__data_o[0];
     endcase
   end
   always @* begin
@@ -50870,12 +50870,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$73  = 1'h0;
+    \fus_src3_i$66  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_so_logical0_1)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$73  = xer_src1__data_o[0];
+          \fus_src3_i$66  = xer_src1__data_o[0];
     endcase
   end
   always @* begin
@@ -50908,12 +50908,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$74  = 1'h0;
+    \fus_src3_i$67  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_so_div0_3)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$74  = xer_src1__data_o[0];
+          \fus_src3_i$67  = xer_src1__data_o[0];
     endcase
   end
   always @* begin
@@ -50927,12 +50927,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$75  = 1'h0;
+    \fus_src3_i$68  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_so_mul0_4)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$75  = xer_src1__data_o[0];
+          \fus_src3_i$68  = xer_src1__data_o[0];
     endcase
   end
   always @* begin
@@ -50946,12 +50946,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src4_i$76  = 1'h0;
+    \fus_src4_i$69  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_so_shiftrot0_5)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src4_i$76  = xer_src1__data_o[0];
+          \fus_src4_i$69  = xer_src1__data_o[0];
     endcase
   end
   always @* begin
@@ -50965,12 +50965,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src4_i$77  = 2'h0;
+    \fus_src4_i$70  = 2'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_ca_alu0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src4_i$77  = xer_src2__data_o;
+          \fus_src4_i$70  = xer_src2__data_o;
     endcase
   end
   always @* begin
@@ -50986,10 +50986,10 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     if (\initial ) begin end
     \counter$next  = counter;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *)
-    casez (\$225 )
+    casez (\$211 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" */
       1'h1:
-          \counter$next  = \$227 [1:0];
+          \counter$next  = \$213 [1:0];
     endcase
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
@@ -51046,7 +51046,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
     if (\initial ) begin end
     corebusy_o = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *)
-    casez (\$230 )
+    casez (\$216 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" */
       1'h1:
           corebusy_o = 1'h1;
@@ -51080,55 +51080,55 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[1])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$14 ;
+                      corebusy_o = \fus_cu_busy_o$7 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[2])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$17 ;
+                      corebusy_o = \fus_cu_busy_o$10 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[3])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$20 ;
+                      corebusy_o = \fus_cu_busy_o$13 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[4])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$23 ;
+                      corebusy_o = \fus_cu_busy_o$16 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[5])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$26 ;
+                      corebusy_o = \fus_cu_busy_o$19 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[6])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$29 ;
+                      corebusy_o = \fus_cu_busy_o$22 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[7])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$32 ;
+                      corebusy_o = \fus_cu_busy_o$25 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[8])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$35 ;
+                      corebusy_o = \fus_cu_busy_o$28 ;
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
                 casez (fu_enable[9])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      corebusy_o = \fus_cu_busy_o$38 ;
+                      corebusy_o = \fus_cu_busy_o$31 ;
                 endcase
               end
           endcase
@@ -51145,12 +51145,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src5_i$78  = 2'h0;
+    \fus_src5_i$71  = 2'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_XER_xer_ov_spr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src5_i$78  = xer_src3__data_o;
+          \fus_src5_i$71  = xer_src3__data_o;
     endcase
   end
   always @* begin
@@ -51185,12 +51185,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$79  = 32'd0;
+    \fus_src3_i$72  = 32'd0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_CR_full_cr_cr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$79  = cr_full_rd__data_o;
+          \fus_src3_i$72  = cr_full_rd__data_o;
     endcase
   end
   always @* begin
@@ -51204,12 +51204,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src4_i$80  = 4'h0;
+    \fus_src4_i$73  = 4'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_CR_cr_a_cr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src4_i$80  = cr_src1__data_o;
+          \fus_src4_i$73  = cr_src1__data_o;
     endcase
   end
   always @* begin
@@ -51253,12 +51253,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$83  = 4'h0;
+    \fus_src3_i$76  = 4'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_CR_cr_a_branch0_1)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$83  = cr_src1__data_o;
+          \fus_src3_i$76  = cr_src1__data_o;
     endcase
   end
   always @* begin
@@ -51302,12 +51302,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src5_i$84  = 4'h0;
+    \fus_src5_i$77  = 4'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_CR_cr_b_cr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src5_i$84  = cr_src2__data_o;
+          \fus_src5_i$77  = cr_src2__data_o;
     endcase
   end
   always @* begin
@@ -51352,12 +51352,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src6_i$85  = 4'h0;
+    \fus_src6_i$78  = 4'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_CR_cr_c_cr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src6_i$85  = cr_src3__data_o;
+          \fus_src6_i$78  = cr_src3__data_o;
     endcase
   end
   always @* begin
@@ -51371,12 +51371,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src1_i$86  = 64'h0000000000000000;
+    \fus_src1_i$79  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_branch0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src1_i$86  = fast_src1__data_o;
+          \fus_src1_i$79  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51390,12 +51390,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$87  = 64'h0000000000000000;
+    \fus_src3_i$80  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_trap0_1)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$87  = fast_src1__data_o;
+          \fus_src3_i$80  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51440,12 +51440,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src3_i$88  = 64'h0000000000000000;
+    \fus_src3_i$81  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_spr0_2)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src3_i$88  = fast_src1__data_o;
+          \fus_src3_i$81  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51459,12 +51459,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$89  = 64'h0000000000000000;
+    \fus_src2_i$82  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_branch0_3)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$89  = fast_src1__data_o;
+          \fus_src2_i$82  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51478,12 +51478,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src4_i$90  = 64'h0000000000000000;
+    \fus_src4_i$83  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_trap0_4)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src4_i$90  = fast_src1__data_o;
+          \fus_src4_i$83  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51497,12 +51497,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src5_i$91  = 64'h0000000000000000;
+    \fus_src5_i$84  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_FAST_fast1_trap0_5)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src5_i$91  = fast_src1__data_o;
+          \fus_src5_i$84  = fast_src1__data_o;
     endcase
   end
   always @* begin
@@ -51547,12 +51547,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_src2_i$92  = 64'h0000000000000000;
+    \fus_src2_i$85  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
     casez (dp_SPR_spr1_spr0_0)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
       1'h1:
-          \fus_src2_i$92  = spr_spr1__data_o;
+          \fus_src2_i$85  = spr_spr1__data_o;
     endcase
   end
   always @* begin
@@ -51566,11 +51566,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1009$next  = \wr_pick$1006 ;
+    \wr_pick_dly$995$next  = \wr_pick$992 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1009$next  = 1'h0;
+          \wr_pick_dly$995$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51605,11 +51605,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1028$next  = \wr_pick$1025 ;
+    \wr_pick_dly$1014$next  = \wr_pick$1011 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1028$next  = 1'h0;
+          \wr_pick_dly$1014$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51644,20 +51644,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1051$next  = \wr_pick$1048 ;
+    \wr_pick_dly$1037$next  = \wr_pick$1034 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1051$next  = 1'h0;
+          \wr_pick_dly$1037$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1069$next  = \wr_pick$1066 ;
+    \wr_pick_dly$1055$next  = \wr_pick$1052 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1069$next  = 1'h0;
+          \wr_pick_dly$1055$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51692,11 +51692,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1091$next  = \wr_pick$1088 ;
+    \wr_pick_dly$1077$next  = \wr_pick$1074 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1091$next  = 1'h0;
+          \wr_pick_dly$1077$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51731,11 +51731,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1111$next  = \wr_pick$1108 ;
+    \wr_pick_dly$1097$next  = \wr_pick$1094 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1111$next  = 1'h0;
+          \wr_pick_dly$1097$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51770,20 +51770,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1131$next  = \wr_pick$1128 ;
+    \wr_pick_dly$1117$next  = \wr_pick$1114 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1131$next  = 1'h0;
+          \wr_pick_dly$1117$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1150$next  = \wr_pick$1147 ;
+    \wr_pick_dly$1136$next  = \wr_pick$1133 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1150$next  = 1'h0;
+          \wr_pick_dly$1136$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51818,11 +51818,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1168$next  = \wr_pick$1165 ;
+    \wr_pick_dly$1154$next  = \wr_pick$1151 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1168$next  = 1'h0;
+          \wr_pick_dly$1154$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51857,11 +51857,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1242$next  = \wr_pick$1239 ;
+    \wr_pick_dly$1228$next  = \wr_pick$1225 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1242$next  = 1'h0;
+          \wr_pick_dly$1228$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51896,20 +51896,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1270$next  = \wr_pick$1267 ;
+    \wr_pick_dly$1256$next  = \wr_pick$1253 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1270$next  = 1'h0;
+          \wr_pick_dly$1256$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1290$next  = \wr_pick$1287 ;
+    \wr_pick_dly$1276$next  = \wr_pick$1273 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1290$next  = 1'h0;
+          \wr_pick_dly$1276$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51944,11 +51944,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1310$next  = \wr_pick$1307 ;
+    \wr_pick_dly$1296$next  = \wr_pick$1293 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1310$next  = 1'h0;
+          \wr_pick_dly$1296$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -51983,20 +51983,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1330$next  = \wr_pick$1327 ;
+    \wr_pick_dly$1316$next  = \wr_pick$1313 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1330$next  = 1'h0;
+          \wr_pick_dly$1316$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1350$next  = \wr_pick$1347 ;
+    \wr_pick_dly$1336$next  = \wr_pick$1333 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1350$next  = 1'h0;
+          \wr_pick_dly$1336$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52031,11 +52031,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1370$next  = \wr_pick$1367 ;
+    \wr_pick_dly$1356$next  = \wr_pick$1353 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1370$next  = 1'h0;
+          \wr_pick_dly$1356$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52070,20 +52070,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1417$next  = \wr_pick$1414 ;
+    \wr_pick_dly$1403$next  = \wr_pick$1400 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1417$next  = 1'h0;
+          \wr_pick_dly$1403$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1433$next  = \wr_pick$1430 ;
+    \wr_pick_dly$1419$next  = \wr_pick$1416 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1433$next  = 1'h0;
+          \wr_pick_dly$1419$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52118,11 +52118,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1449$next  = \wr_pick$1446 ;
+    \wr_pick_dly$1435$next  = \wr_pick$1432 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1449$next  = 1'h0;
+          \wr_pick_dly$1435$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52157,20 +52157,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1483$next  = \wr_pick$1480 ;
+    \wr_pick_dly$1469$next  = \wr_pick$1466 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1483$next  = 1'h0;
+          \wr_pick_dly$1469$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1499$next  = \wr_pick$1496 ;
+    \wr_pick_dly$1485$next  = \wr_pick$1482 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1499$next  = 1'h0;
+          \wr_pick_dly$1485$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52205,11 +52205,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1515$next  = \wr_pick$1512 ;
+    \wr_pick_dly$1501$next  = \wr_pick$1498 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1515$next  = 1'h0;
+          \wr_pick_dly$1501$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52237,18 +52237,18 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[0])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      fus_cu_rdmaskn_i = \$232 ;
+                      fus_cu_rdmaskn_i = \$218 ;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1531$next  = \wr_pick$1528 ;
+    \wr_pick_dly$1517$next  = \wr_pick$1514 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1531$next  = 1'h0;
+          \wr_pick_dly$1517$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52283,20 +52283,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1567$next  = \wr_pick$1564 ;
+    \wr_pick_dly$1553$next  = \wr_pick$1550 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1567$next  = 1'h0;
+          \wr_pick_dly$1553$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1583$next  = \wr_pick$1580 ;
+    \wr_pick_dly$1569$next  = \wr_pick$1566 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1583$next  = 1'h0;
+          \wr_pick_dly$1569$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52331,20 +52331,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1599$next  = \wr_pick$1596 ;
+    \wr_pick_dly$1585$next  = \wr_pick$1582 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1599$next  = 1'h0;
+          \wr_pick_dly$1585$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1615$next  = \wr_pick$1612 ;
+    \wr_pick_dly$1601$next  = \wr_pick$1598 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1615$next  = 1'h0;
+          \wr_pick_dly$1601$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52379,11 +52379,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1659$next  = \wr_pick$1656 ;
+    \wr_pick_dly$1645$next  = \wr_pick$1642 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1659$next  = 1'h0;
+          \wr_pick_dly$1645$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52418,11 +52418,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1678$next  = \wr_pick$1675 ;
+    \wr_pick_dly$1664$next  = \wr_pick$1661 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1678$next  = 1'h0;
+          \wr_pick_dly$1664$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52457,20 +52457,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1694$next  = \wr_pick$1691 ;
+    \wr_pick_dly$1680$next  = \wr_pick$1677 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1694$next  = 1'h0;
+          \wr_pick_dly$1680$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1710$next  = \wr_pick$1707 ;
+    \wr_pick_dly$1696$next  = \wr_pick$1693 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1710$next  = 1'h0;
+          \wr_pick_dly$1696$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52505,20 +52505,20 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1726$next  = \wr_pick$1723 ;
+    \wr_pick_dly$1712$next  = \wr_pick$1709 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1726$next  = 1'h0;
+          \wr_pick_dly$1712$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1742$next  = \wr_pick$1739 ;
+    \wr_pick_dly$1728$next  = \wr_pick$1725 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1742$next  = 1'h0;
+          \wr_pick_dly$1728$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52553,16 +52553,16 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1794$next  = \wr_pick$1791 ;
+    \wr_pick_dly$1780$next  = \wr_pick$1777 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1794$next  = 1'h0;
+          \wr_pick_dly$1780$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$13  = 1'h0;
+    \fus_cu_issue_i$6  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -52585,23 +52585,23 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[1])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$13  = issue_i;
+                      \fus_cu_issue_i$6  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1810$next  = \wr_pick$1807 ;
+    \wr_pick_dly$1796$next  = \wr_pick$1793 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1810$next  = 1'h0;
+          \wr_pick_dly$1796$next  = 1'h0;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$15  = 6'h00;
+    \fus_cu_rdmaskn_i$8  = 6'h00;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -52624,18 +52624,18 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[1])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$15  = \$254 ;
+                      \fus_cu_rdmaskn_i$8  = \$240 ;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1834$next  = \wr_pick$1831 ;
+    \wr_pick_dly$1820$next  = \wr_pick$1817 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1834$next  = 1'h0;
+          \wr_pick_dly$1820$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52670,11 +52670,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1854$next  = \wr_pick$1851 ;
+    \wr_pick_dly$1840$next  = \wr_pick$1837 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1854$next  = 1'h0;
+          \wr_pick_dly$1840$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52709,11 +52709,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \wr_pick_dly$1874$next  = \wr_pick$1871 ;
+    \wr_pick_dly$1860$next  = \wr_pick$1857 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \wr_pick_dly$1874$next  = 1'h0;
+          \wr_pick_dly$1860$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -52989,7 +52989,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_issue_i$16  = 1'h0;
+    \fus_cu_issue_i$9  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -53012,14 +53012,14 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[2])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_issue_i$16  = issue_i;
+                      \fus_cu_issue_i$9  = issue_i;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \fus_cu_rdmaskn_i$18  = 3'h0;
+    \fus_cu_rdmaskn_i$11  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
     casez (ivalid_i)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
@@ -53042,7 +53042,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[2])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      \fus_cu_rdmaskn_i$18  = \$256 ;
+                      \fus_cu_rdmaskn_i$11  = \$242 ;
                 endcase
           endcase
     endcase
@@ -53342,7 +53342,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
                 casez (fu_enable[3])
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
                   1'h1:
-                      fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal  };
+                      fus_oper_i_alu_trap0__ldst_exc = { core_core_exc_happened, core_core_exc_segment_fault, core_core_exc_rc_error, core_core_exc_perm_error, core_core_exc_badtree, core_core_exc_invalid, core_core_exc_instr_fault, core_core_exc_alignment };
                 endcase
           endcase
     endcase
@@ -53407,12 +53407,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
           endcase
     endcase
   end
-  assign \$227  = \$228 ;
-  assign \$584  = \$619 ;
-  assign \$833  = \$834 ;
-  assign \$1179  = \$1196 ;
-  assign \$1198  = \$1215 ;
-  assign \$1395  = \$1404 ;
+  assign \$213  = \$214 ;
+  assign \$570  = \$605 ;
+  assign \$819  = \$820 ;
+  assign \$1165  = \$1182 ;
+  assign \$1184  = \$1201 ;
+  assign \$1381  = \$1390 ;
   assign sv_a_nz = 1'h0;
   assign ALU__sv_pred_sz = 1'h0;
   assign ALU__sv_pred_dz = 1'h0;
@@ -53452,509 +53452,509 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   assign LDST__SV_Ptype = 2'h0;
   assign o_ok = 1'h0;
   assign ea_ok = 1'h0;
-  assign spr_spr1__wen = \wp$1879 ;
-  assign \spr_spr1__addr$179  = \addr_en$1882 [3:0];
-  assign spr_spr1__data_i = \fus_dest2_o$164 ;
-  assign \addr_en$1882  = \$1883 ;
-  assign \wp$1879  = \$1880 ;
-  assign \wr_pick_rise$1079  = \$1877 ;
-  assign \wr_pick$1871  = \$1872 ;
-  assign wrpick_SPR_spr1_i = \$1869 ;
-  assign wrflag_spr0_spr1_1 = \$1867 ;
-  assign \state_wen$178  = \addr_en$1862 ;
-  assign \state_data_i$177  = \$1865 ;
-  assign \addr_en$1862  = \$1863 ;
-  assign \wp$1859  = \$1860 ;
-  assign \wr_pick_rise$1039  = \$1857 ;
-  assign \wr_pick$1851  = \$1852 ;
-  assign wrpick_STATE_svstate_i = \$1849 ;
-  assign wrflag_trap0_svstate_6 = \$1847 ;
-  assign state_wen = \$1845 ;
-  assign \state_data_i$176  = \fus_dest6_o$163 ;
-  assign \addr_en$1842  = \$1843 ;
-  assign \wp$1839  = \$1840 ;
-  assign \wr_pick_rise$1038  = \$1837 ;
-  assign \wr_pick$1831  = \$1832 ;
-  assign wrpick_STATE_msr_i = \$1829 ;
-  assign wrflag_trap0_msr_5 = \$1827 ;
-  assign state_nia_wen = \$1823 ;
-  assign state_data_i = \$1821 ;
-  assign \addr_en$1818  = \$1819 ;
-  assign \wp$1815  = \$1816 ;
-  assign \wr_pick_rise$1037  = \$1813 ;
-  assign \wr_pick$1807  = \$1808 ;
-  assign wrflag_trap0_nia_4 = \$1805 ;
-  assign \addr_en$1802  = \$1803 ;
-  assign \wp$1799  = \$1800 ;
-  assign \wr_pick_rise$1666  = \$1797 ;
-  assign \wr_pick$1791  = \$1792 ;
-  assign wrpick_STATE_nia_i[1] = \$1789 ;
-  assign wrpick_STATE_nia_i[0] = \$1787 ;
-  assign wrflag_branch0_nia_2 = \$1785 ;
-  assign fast_dest1__wen = \$1783 ;
-  assign fast_dest1__addr = \$1763 ;
-  assign fast_dest1__data_i = \$1761 ;
-  assign \addr_en$1750  = \$1751 ;
-  assign \wp$1747  = \$1748 ;
-  assign \wr_pick_rise$1036  = \$1745 ;
-  assign \wr_pick$1739  = \$1740 ;
-  assign wrflag_trap0_fast1_3 = \$1737 ;
-  assign \addr_en$1734  = \$1735 ;
-  assign \wp$1731  = \$1732 ;
-  assign \wr_pick_rise$1035  = \$1729 ;
-  assign \wr_pick$1723  = \$1724 ;
-  assign wrflag_trap0_fast1_2 = \$1721 ;
-  assign \addr_en$1718  = \$1719 ;
-  assign \wp$1715  = \$1716 ;
-  assign \wr_pick_rise$1665  = \$1713 ;
-  assign \wr_pick$1707  = \$1708 ;
-  assign wrflag_branch0_fast1_1 = \$1705 ;
-  assign \addr_en$1702  = \$1703 ;
-  assign \wp$1699  = \$1700 ;
-  assign \wr_pick_rise$1078  = \$1697 ;
-  assign \wr_pick$1691  = \$1692 ;
-  assign wrflag_spr0_fast1_2 = \$1689 ;
-  assign \addr_en$1686  = \$1687 ;
-  assign \wp$1683  = \$1684 ;
-  assign \wr_pick_rise$1034  = \$1681 ;
-  assign \wr_pick$1675  = \$1676 ;
-  assign wrflag_trap0_fast1_1 = \$1673 ;
-  assign \addr_en$1670  = \$1671 ;
-  assign \wp$1667  = \$1668 ;
-  assign \fus_cu_wr__go_i$150 [2] = \wr_pick_rise$1666 ;
-  assign \fus_cu_wr__go_i$150 [1] = \wr_pick_rise$1665 ;
-  assign \fus_cu_wr__go_i$150 [0] = \wr_pick_rise$1660 ;
-  assign \wr_pick_rise$1660  = \$1663 ;
-  assign \wr_pick$1656  = \$1657 ;
-  assign wrpick_FAST_fast1_i[5] = \$1654 ;
-  assign wrpick_FAST_fast1_i[4] = \$1652 ;
-  assign wrpick_FAST_fast1_i[3] = \$1650 ;
-  assign wrpick_FAST_fast1_i[2] = \$1648 ;
-  assign wrpick_FAST_fast1_i[1] = \$1646 ;
-  assign wrpick_FAST_fast1_i[0] = \$1644 ;
-  assign wrflag_branch0_fast1_0 = \$1642 ;
-  assign \xer_wen$175  = \$1634 ;
-  assign \xer_data_i$174  = \$1626 ;
-  assign \addr_en$1623  = \$1624 ;
-  assign \wp$1620  = \$1621 ;
-  assign \wr_pick_rise$1119  = \$1618 ;
-  assign \wr_pick$1612  = \$1613 ;
-  assign wrflag_mul0_xer_so_3 = \$1610 ;
-  assign \addr_en$1607  = \$1608 ;
-  assign \wp$1604  = \$1605 ;
-  assign \wr_pick_rise$1099  = \$1602 ;
-  assign \wr_pick$1596  = \$1597 ;
-  assign wrflag_div0_xer_so_3 = \$1594 ;
-  assign \addr_en$1591  = \$1592 ;
-  assign \wp$1588  = \$1589 ;
-  assign \wr_pick_rise$1077  = \$1586 ;
-  assign \wr_pick$1580  = \$1581 ;
-  assign wrflag_spr0_xer_so_3 = \$1578 ;
-  assign \addr_en$1575  = \$1576 ;
-  assign \wp$1572  = \$1573 ;
-  assign \wr_pick_rise$999  = \$1570 ;
-  assign \wr_pick$1564  = \$1565 ;
-  assign wrpick_XER_xer_so_i[3] = \$1562 ;
-  assign wrpick_XER_xer_so_i[2] = \$1560 ;
-  assign wrpick_XER_xer_so_i[1] = \$1558 ;
-  assign wrpick_XER_xer_so_i[0] = \$1556 ;
-  assign wrflag_alu0_xer_so_4 = \$1554 ;
-  assign \xer_wen$173  = \$1552 ;
-  assign \xer_data_i$172  = \$1546 ;
-  assign \addr_en$1539  = \$1540 ;
-  assign \wp$1536  = \$1537 ;
-  assign \wr_pick_rise$1118  = \$1534 ;
-  assign \wr_pick$1528  = \$1529 ;
-  assign wrflag_mul0_xer_ov_2 = \$1526 ;
-  assign \addr_en$1523  = \$1524 ;
-  assign \wp$1520  = \$1521 ;
-  assign \wr_pick_rise$1098  = \$1518 ;
-  assign \wr_pick$1512  = \$1513 ;
-  assign wrflag_div0_xer_ov_2 = \$1510 ;
-  assign \addr_en$1507  = \$1508 ;
-  assign \wp$1504  = \$1505 ;
-  assign \wr_pick_rise$1076  = \$1502 ;
-  assign \wr_pick$1496  = \$1497 ;
-  assign wrflag_spr0_xer_ov_4 = \$1494 ;
-  assign \addr_en$1491  = \$1492 ;
-  assign \wp$1488  = \$1489 ;
-  assign \wr_pick_rise$998  = \$1486 ;
-  assign \wr_pick$1480  = \$1481 ;
-  assign wrpick_XER_xer_ov_i[3] = \$1478 ;
-  assign wrpick_XER_xer_ov_i[2] = \$1476 ;
-  assign wrpick_XER_xer_ov_i[1] = \$1474 ;
-  assign wrpick_XER_xer_ov_i[0] = \$1472 ;
-  assign wrflag_alu0_xer_ov_3 = \$1470 ;
-  assign xer_wen = \$1464 ;
-  assign xer_data_i = \$1462 ;
-  assign \addr_en$1457  = \$1458 ;
-  assign \wp$1454  = \$1455 ;
-  assign \wr_pick_rise$1138  = \$1452 ;
-  assign \wr_pick$1446  = \$1447 ;
-  assign wrflag_shiftrot0_xer_ca_2 = \$1444 ;
-  assign \addr_en$1441  = \$1442 ;
-  assign \wp$1438  = \$1439 ;
-  assign \wr_pick_rise$1075  = \$1436 ;
-  assign \wr_pick$1430  = \$1431 ;
-  assign wrflag_spr0_xer_ca_5 = \$1428 ;
-  assign \addr_en$1425  = \$1426 ;
-  assign \wp$1422  = \$1423 ;
-  assign \wr_pick_rise$997  = \$1420 ;
-  assign \wr_pick$1414  = \$1415 ;
-  assign wrpick_XER_xer_ca_i[2] = \$1412 ;
-  assign wrpick_XER_xer_ca_i[1] = \$1410 ;
-  assign wrpick_XER_xer_ca_i[0] = \$1408 ;
-  assign wrflag_alu0_xer_ca_2 = \$1406 ;
-  assign cr_wen = \$1404 [7:0];
-  assign cr_data_i = \$1393 ;
-  assign \addr_en$1378  = \$1383 ;
-  assign \wp$1375  = \$1376 ;
-  assign \wr_pick_rise$1137  = \$1373 ;
-  assign \wr_pick$1367  = \$1368 ;
-  assign wrflag_shiftrot0_cr_a_1 = \$1365 ;
-  assign \addr_en$1358  = \$1363 ;
-  assign \wp$1355  = \$1356 ;
-  assign \wr_pick_rise$1117  = \$1353 ;
-  assign \wr_pick$1347  = \$1348 ;
-  assign wrflag_mul0_cr_a_1 = \$1345 ;
-  assign \addr_en$1338  = \$1343 ;
-  assign \wp$1335  = \$1336 ;
-  assign \wr_pick_rise$1097  = \$1333 ;
-  assign \wr_pick$1327  = \$1328 ;
-  assign wrflag_div0_cr_a_1 = \$1325 ;
-  assign \addr_en$1318  = \$1323 ;
-  assign \wp$1315  = \$1316 ;
-  assign \wr_pick_rise$1057  = \$1313 ;
-  assign \wr_pick$1307  = \$1308 ;
-  assign wrflag_logical0_cr_a_1 = \$1305 ;
-  assign \addr_en$1298  = \$1303 ;
-  assign \wp$1295  = \$1296 ;
-  assign \wr_pick_rise$1016  = \$1293 ;
-  assign \wr_pick$1287  = \$1288 ;
-  assign wrflag_cr0_cr_a_2 = \$1285 ;
-  assign \addr_en$1278  = \$1283 ;
-  assign \wp$1275  = \$1276 ;
-  assign \wr_pick_rise$996  = \$1273 ;
-  assign \wr_pick$1267  = \$1268 ;
-  assign wrpick_CR_cr_a_i[5] = \$1265 ;
-  assign wrpick_CR_cr_a_i[4] = \$1263 ;
-  assign wrpick_CR_cr_a_i[3] = \$1261 ;
-  assign wrpick_CR_cr_a_i[2] = \$1259 ;
-  assign wrpick_CR_cr_a_i[1] = \$1257 ;
-  assign wrpick_CR_cr_a_i[0] = \$1255 ;
-  assign wrflag_alu0_cr_a_1 = \$1253 ;
-  assign cr_full_wr__wen = \addr_en$1250 ;
+  assign spr_spr1__wen = \wp$1865 ;
+  assign \spr_spr1__addr$165  = \addr_en$1868 [3:0];
+  assign spr_spr1__data_i = \fus_dest2_o$157 ;
+  assign \addr_en$1868  = \$1869 ;
+  assign \wp$1865  = \$1866 ;
+  assign \wr_pick_rise$1065  = \$1863 ;
+  assign \wr_pick$1857  = \$1858 ;
+  assign wrpick_SPR_spr1_i = \$1855 ;
+  assign wrflag_spr0_spr1_1 = \$1853 ;
+  assign \state_wen$164  = \addr_en$1848 ;
+  assign \state_data_i$163  = \$1851 ;
+  assign \addr_en$1848  = \$1849 ;
+  assign \wp$1845  = \$1846 ;
+  assign \wr_pick_rise$1025  = \$1843 ;
+  assign \wr_pick$1837  = \$1838 ;
+  assign wrpick_STATE_svstate_i = \$1835 ;
+  assign wrflag_trap0_svstate_6 = \$1833 ;
+  assign state_wen = \$1831 ;
+  assign \state_data_i$162  = \fus_dest6_o$156 ;
+  assign \addr_en$1828  = \$1829 ;
+  assign \wp$1825  = \$1826 ;
+  assign \wr_pick_rise$1024  = \$1823 ;
+  assign \wr_pick$1817  = \$1818 ;
+  assign wrpick_STATE_msr_i = \$1815 ;
+  assign wrflag_trap0_msr_5 = \$1813 ;
+  assign state_nia_wen = \$1809 ;
+  assign state_data_i = \$1807 ;
+  assign \addr_en$1804  = \$1805 ;
+  assign \wp$1801  = \$1802 ;
+  assign \wr_pick_rise$1023  = \$1799 ;
+  assign \wr_pick$1793  = \$1794 ;
+  assign wrflag_trap0_nia_4 = \$1791 ;
+  assign \addr_en$1788  = \$1789 ;
+  assign \wp$1785  = \$1786 ;
+  assign \wr_pick_rise$1652  = \$1783 ;
+  assign \wr_pick$1777  = \$1778 ;
+  assign wrpick_STATE_nia_i[1] = \$1775 ;
+  assign wrpick_STATE_nia_i[0] = \$1773 ;
+  assign wrflag_branch0_nia_2 = \$1771 ;
+  assign fast_dest1__wen = \$1769 ;
+  assign fast_dest1__addr = \$1749 ;
+  assign fast_dest1__data_i = \$1747 ;
+  assign \addr_en$1736  = \$1737 ;
+  assign \wp$1733  = \$1734 ;
+  assign \wr_pick_rise$1022  = \$1731 ;
+  assign \wr_pick$1725  = \$1726 ;
+  assign wrflag_trap0_fast1_3 = \$1723 ;
+  assign \addr_en$1720  = \$1721 ;
+  assign \wp$1717  = \$1718 ;
+  assign \wr_pick_rise$1021  = \$1715 ;
+  assign \wr_pick$1709  = \$1710 ;
+  assign wrflag_trap0_fast1_2 = \$1707 ;
+  assign \addr_en$1704  = \$1705 ;
+  assign \wp$1701  = \$1702 ;
+  assign \wr_pick_rise$1651  = \$1699 ;
+  assign \wr_pick$1693  = \$1694 ;
+  assign wrflag_branch0_fast1_1 = \$1691 ;
+  assign \addr_en$1688  = \$1689 ;
+  assign \wp$1685  = \$1686 ;
+  assign \wr_pick_rise$1064  = \$1683 ;
+  assign \wr_pick$1677  = \$1678 ;
+  assign wrflag_spr0_fast1_2 = \$1675 ;
+  assign \addr_en$1672  = \$1673 ;
+  assign \wp$1669  = \$1670 ;
+  assign \wr_pick_rise$1020  = \$1667 ;
+  assign \wr_pick$1661  = \$1662 ;
+  assign wrflag_trap0_fast1_1 = \$1659 ;
+  assign \addr_en$1656  = \$1657 ;
+  assign \wp$1653  = \$1654 ;
+  assign \fus_cu_wr__go_i$143 [2] = \wr_pick_rise$1652 ;
+  assign \fus_cu_wr__go_i$143 [1] = \wr_pick_rise$1651 ;
+  assign \fus_cu_wr__go_i$143 [0] = \wr_pick_rise$1646 ;
+  assign \wr_pick_rise$1646  = \$1649 ;
+  assign \wr_pick$1642  = \$1643 ;
+  assign wrpick_FAST_fast1_i[5] = \$1640 ;
+  assign wrpick_FAST_fast1_i[4] = \$1638 ;
+  assign wrpick_FAST_fast1_i[3] = \$1636 ;
+  assign wrpick_FAST_fast1_i[2] = \$1634 ;
+  assign wrpick_FAST_fast1_i[1] = \$1632 ;
+  assign wrpick_FAST_fast1_i[0] = \$1630 ;
+  assign wrflag_branch0_fast1_0 = \$1628 ;
+  assign \xer_wen$161  = \$1620 ;
+  assign \xer_data_i$160  = \$1612 ;
+  assign \addr_en$1609  = \$1610 ;
+  assign \wp$1606  = \$1607 ;
+  assign \wr_pick_rise$1105  = \$1604 ;
+  assign \wr_pick$1598  = \$1599 ;
+  assign wrflag_mul0_xer_so_3 = \$1596 ;
+  assign \addr_en$1593  = \$1594 ;
+  assign \wp$1590  = \$1591 ;
+  assign \wr_pick_rise$1085  = \$1588 ;
+  assign \wr_pick$1582  = \$1583 ;
+  assign wrflag_div0_xer_so_3 = \$1580 ;
+  assign \addr_en$1577  = \$1578 ;
+  assign \wp$1574  = \$1575 ;
+  assign \wr_pick_rise$1063  = \$1572 ;
+  assign \wr_pick$1566  = \$1567 ;
+  assign wrflag_spr0_xer_so_3 = \$1564 ;
+  assign \addr_en$1561  = \$1562 ;
+  assign \wp$1558  = \$1559 ;
+  assign \wr_pick_rise$985  = \$1556 ;
+  assign \wr_pick$1550  = \$1551 ;
+  assign wrpick_XER_xer_so_i[3] = \$1548 ;
+  assign wrpick_XER_xer_so_i[2] = \$1546 ;
+  assign wrpick_XER_xer_so_i[1] = \$1544 ;
+  assign wrpick_XER_xer_so_i[0] = \$1542 ;
+  assign wrflag_alu0_xer_so_4 = \$1540 ;
+  assign \xer_wen$159  = \$1538 ;
+  assign \xer_data_i$158  = \$1532 ;
+  assign \addr_en$1525  = \$1526 ;
+  assign \wp$1522  = \$1523 ;
+  assign \wr_pick_rise$1104  = \$1520 ;
+  assign \wr_pick$1514  = \$1515 ;
+  assign wrflag_mul0_xer_ov_2 = \$1512 ;
+  assign \addr_en$1509  = \$1510 ;
+  assign \wp$1506  = \$1507 ;
+  assign \wr_pick_rise$1084  = \$1504 ;
+  assign \wr_pick$1498  = \$1499 ;
+  assign wrflag_div0_xer_ov_2 = \$1496 ;
+  assign \addr_en$1493  = \$1494 ;
+  assign \wp$1490  = \$1491 ;
+  assign \wr_pick_rise$1062  = \$1488 ;
+  assign \wr_pick$1482  = \$1483 ;
+  assign wrflag_spr0_xer_ov_4 = \$1480 ;
+  assign \addr_en$1477  = \$1478 ;
+  assign \wp$1474  = \$1475 ;
+  assign \wr_pick_rise$984  = \$1472 ;
+  assign \wr_pick$1466  = \$1467 ;
+  assign wrpick_XER_xer_ov_i[3] = \$1464 ;
+  assign wrpick_XER_xer_ov_i[2] = \$1462 ;
+  assign wrpick_XER_xer_ov_i[1] = \$1460 ;
+  assign wrpick_XER_xer_ov_i[0] = \$1458 ;
+  assign wrflag_alu0_xer_ov_3 = \$1456 ;
+  assign xer_wen = \$1450 ;
+  assign xer_data_i = \$1448 ;
+  assign \addr_en$1443  = \$1444 ;
+  assign \wp$1440  = \$1441 ;
+  assign \wr_pick_rise$1124  = \$1438 ;
+  assign \wr_pick$1432  = \$1433 ;
+  assign wrflag_shiftrot0_xer_ca_2 = \$1430 ;
+  assign \addr_en$1427  = \$1428 ;
+  assign \wp$1424  = \$1425 ;
+  assign \wr_pick_rise$1061  = \$1422 ;
+  assign \wr_pick$1416  = \$1417 ;
+  assign wrflag_spr0_xer_ca_5 = \$1414 ;
+  assign \addr_en$1411  = \$1412 ;
+  assign \wp$1408  = \$1409 ;
+  assign \wr_pick_rise$983  = \$1406 ;
+  assign \wr_pick$1400  = \$1401 ;
+  assign wrpick_XER_xer_ca_i[2] = \$1398 ;
+  assign wrpick_XER_xer_ca_i[1] = \$1396 ;
+  assign wrpick_XER_xer_ca_i[0] = \$1394 ;
+  assign wrflag_alu0_xer_ca_2 = \$1392 ;
+  assign cr_wen = \$1390 [7:0];
+  assign cr_data_i = \$1379 ;
+  assign \addr_en$1364  = \$1369 ;
+  assign \wp$1361  = \$1362 ;
+  assign \wr_pick_rise$1123  = \$1359 ;
+  assign \wr_pick$1353  = \$1354 ;
+  assign wrflag_shiftrot0_cr_a_1 = \$1351 ;
+  assign \addr_en$1344  = \$1349 ;
+  assign \wp$1341  = \$1342 ;
+  assign \wr_pick_rise$1103  = \$1339 ;
+  assign \wr_pick$1333  = \$1334 ;
+  assign wrflag_mul0_cr_a_1 = \$1331 ;
+  assign \addr_en$1324  = \$1329 ;
+  assign \wp$1321  = \$1322 ;
+  assign \wr_pick_rise$1083  = \$1319 ;
+  assign \wr_pick$1313  = \$1314 ;
+  assign wrflag_div0_cr_a_1 = \$1311 ;
+  assign \addr_en$1304  = \$1309 ;
+  assign \wp$1301  = \$1302 ;
+  assign \wr_pick_rise$1043  = \$1299 ;
+  assign \wr_pick$1293  = \$1294 ;
+  assign wrflag_logical0_cr_a_1 = \$1291 ;
+  assign \addr_en$1284  = \$1289 ;
+  assign \wp$1281  = \$1282 ;
+  assign \wr_pick_rise$1002  = \$1279 ;
+  assign \wr_pick$1273  = \$1274 ;
+  assign wrflag_cr0_cr_a_2 = \$1271 ;
+  assign \addr_en$1264  = \$1269 ;
+  assign \wp$1261  = \$1262 ;
+  assign \wr_pick_rise$982  = \$1259 ;
+  assign \wr_pick$1253  = \$1254 ;
+  assign wrpick_CR_cr_a_i[5] = \$1251 ;
+  assign wrpick_CR_cr_a_i[4] = \$1249 ;
+  assign wrpick_CR_cr_a_i[3] = \$1247 ;
+  assign wrpick_CR_cr_a_i[2] = \$1245 ;
+  assign wrpick_CR_cr_a_i[1] = \$1243 ;
+  assign wrpick_CR_cr_a_i[0] = \$1241 ;
+  assign wrflag_alu0_cr_a_1 = \$1239 ;
+  assign cr_full_wr__wen = \addr_en$1236 ;
   assign cr_full_wr__data_i = fus_dest2_o;
-  assign \addr_en$1250  = \$1251 ;
-  assign \wp$1247  = \$1248 ;
-  assign \wr_pick_rise$1015  = \$1245 ;
-  assign \wr_pick$1239  = \$1240 ;
-  assign wrpick_CR_full_cr_i = \$1237 ;
-  assign wrflag_cr0_full_cr_1 = \$1235 ;
-  assign int_dest1__wen = \$1233 ;
-  assign int_dest1__addr = \$1215 [4:0];
-  assign int_dest1__data_i = \$1196 [63:0];
-  assign \addr_en$1176  = \$1177 ;
-  assign \wp$1173  = \$1174 ;
-  assign \wr_pick_rise$1156  = \$1171 ;
-  assign \wr_pick$1165  = \$1166 ;
-  assign wrflag_ldst0_o_1 = \$1163 ;
-  assign \addr_en$1160  = \$1161 ;
-  assign \wp$1157  = \$1158 ;
-  assign \fus_cu_wr__go_i$115 [1] = \wr_pick_rise$1156 ;
-  assign \fus_cu_wr__go_i$115 [0] = \wr_pick_rise$1151 ;
-  assign \wr_pick_rise$1151  = \$1154 ;
-  assign \wr_pick$1147  = \$1148 ;
-  assign wrflag_ldst0_o_0 = \$1145 ;
-  assign \addr_en$1142  = \$1143 ;
-  assign \wp$1139  = \$1140 ;
-  assign \fus_cu_wr__go_i$113 [2] = \wr_pick_rise$1138 ;
-  assign \fus_cu_wr__go_i$113 [1] = \wr_pick_rise$1137 ;
-  assign \fus_cu_wr__go_i$113 [0] = \wr_pick_rise$1132 ;
-  assign \wr_pick_rise$1132  = \$1135 ;
-  assign \wr_pick$1128  = \$1129 ;
-  assign wrflag_shiftrot0_o_0 = \$1126 ;
-  assign \addr_en$1123  = \$1124 ;
-  assign \wp$1120  = \$1121 ;
-  assign \fus_cu_wr__go_i$110 [3] = \wr_pick_rise$1119 ;
-  assign \fus_cu_wr__go_i$110 [2] = \wr_pick_rise$1118 ;
-  assign \fus_cu_wr__go_i$110 [1] = \wr_pick_rise$1117 ;
-  assign \fus_cu_wr__go_i$110 [0] = \wr_pick_rise$1112 ;
-  assign \wr_pick_rise$1112  = \$1115 ;
-  assign \wr_pick$1108  = \$1109 ;
-  assign wrflag_mul0_o_0 = \$1106 ;
-  assign \addr_en$1103  = \$1104 ;
-  assign \wp$1100  = \$1101 ;
-  assign \fus_cu_wr__go_i$107 [3] = \wr_pick_rise$1099 ;
-  assign \fus_cu_wr__go_i$107 [2] = \wr_pick_rise$1098 ;
-  assign \fus_cu_wr__go_i$107 [1] = \wr_pick_rise$1097 ;
-  assign \fus_cu_wr__go_i$107 [0] = \wr_pick_rise$1092 ;
-  assign \wr_pick_rise$1092  = \$1095 ;
-  assign \wr_pick$1088  = \$1089 ;
-  assign wrflag_div0_o_0 = \$1086 ;
-  assign \addr_en$1083  = \$1084 ;
-  assign \wp$1080  = \$1081 ;
-  assign \fus_cu_wr__go_i$104 [1] = \wr_pick_rise$1079 ;
-  assign \fus_cu_wr__go_i$104 [2] = \wr_pick_rise$1078 ;
-  assign \fus_cu_wr__go_i$104 [3] = \wr_pick_rise$1077 ;
-  assign \fus_cu_wr__go_i$104 [4] = \wr_pick_rise$1076 ;
-  assign \fus_cu_wr__go_i$104 [5] = \wr_pick_rise$1075 ;
-  assign \fus_cu_wr__go_i$104 [0] = \wr_pick_rise$1070 ;
-  assign \wr_pick_rise$1070  = \$1073 ;
-  assign \wr_pick$1066  = \$1067 ;
-  assign wrflag_spr0_o_0 = \$1064 ;
-  assign \addr_en$1061  = \$1062 ;
-  assign \wp$1058  = \$1059 ;
-  assign \fus_cu_wr__go_i$101 [1] = \wr_pick_rise$1057 ;
-  assign \fus_cu_wr__go_i$101 [0] = \wr_pick_rise$1052 ;
-  assign \wr_pick_rise$1052  = \$1055 ;
-  assign \wr_pick$1048  = \$1049 ;
-  assign wrflag_logical0_o_0 = \$1046 ;
-  assign \addr_en$1043  = \$1044 ;
-  assign \wp$1040  = \$1041 ;
-  assign \fus_cu_wr__go_i$98 [6] = \wr_pick_rise$1039 ;
-  assign \fus_cu_wr__go_i$98 [5] = \wr_pick_rise$1038 ;
-  assign \fus_cu_wr__go_i$98 [4] = \wr_pick_rise$1037 ;
-  assign \fus_cu_wr__go_i$98 [3] = \wr_pick_rise$1036 ;
-  assign \fus_cu_wr__go_i$98 [2] = \wr_pick_rise$1035 ;
-  assign \fus_cu_wr__go_i$98 [1] = \wr_pick_rise$1034 ;
-  assign \fus_cu_wr__go_i$98 [0] = \wr_pick_rise$1029 ;
-  assign \wr_pick_rise$1029  = \$1032 ;
-  assign \wr_pick$1025  = \$1026 ;
-  assign wrflag_trap0_o_0 = \$1023 ;
-  assign \addr_en$1020  = \$1021 ;
-  assign \wp$1017  = \$1018 ;
-  assign \fus_cu_wr__go_i$95 [2] = \wr_pick_rise$1016 ;
-  assign \fus_cu_wr__go_i$95 [1] = \wr_pick_rise$1015 ;
-  assign \fus_cu_wr__go_i$95 [0] = \wr_pick_rise$1010 ;
-  assign \wr_pick_rise$1010  = \$1013 ;
-  assign \wr_pick$1006  = \$1007 ;
-  assign wrflag_cr0_o_0 = \$1004 ;
-  assign addr_en = \$1002 ;
-  assign wp = \$1000 ;
-  assign fus_cu_wr__go_i[4] = \wr_pick_rise$999 ;
-  assign fus_cu_wr__go_i[3] = \wr_pick_rise$998 ;
-  assign fus_cu_wr__go_i[2] = \wr_pick_rise$997 ;
-  assign fus_cu_wr__go_i[1] = \wr_pick_rise$996 ;
+  assign \addr_en$1236  = \$1237 ;
+  assign \wp$1233  = \$1234 ;
+  assign \wr_pick_rise$1001  = \$1231 ;
+  assign \wr_pick$1225  = \$1226 ;
+  assign wrpick_CR_full_cr_i = \$1223 ;
+  assign wrflag_cr0_full_cr_1 = \$1221 ;
+  assign int_dest1__wen = \$1219 ;
+  assign int_dest1__addr = \$1201 [4:0];
+  assign int_dest1__data_i = \$1182 [63:0];
+  assign \addr_en$1162  = \$1163 ;
+  assign \wp$1159  = \$1160 ;
+  assign \wr_pick_rise$1142  = \$1157 ;
+  assign \wr_pick$1151  = \$1152 ;
+  assign wrflag_ldst0_o_1 = \$1149 ;
+  assign \addr_en$1146  = \$1147 ;
+  assign \wp$1143  = \$1144 ;
+  assign \fus_cu_wr__go_i$108 [1] = \wr_pick_rise$1142 ;
+  assign \fus_cu_wr__go_i$108 [0] = \wr_pick_rise$1137 ;
+  assign \wr_pick_rise$1137  = \$1140 ;
+  assign \wr_pick$1133  = \$1134 ;
+  assign wrflag_ldst0_o_0 = \$1131 ;
+  assign \addr_en$1128  = \$1129 ;
+  assign \wp$1125  = \$1126 ;
+  assign \fus_cu_wr__go_i$106 [2] = \wr_pick_rise$1124 ;
+  assign \fus_cu_wr__go_i$106 [1] = \wr_pick_rise$1123 ;
+  assign \fus_cu_wr__go_i$106 [0] = \wr_pick_rise$1118 ;
+  assign \wr_pick_rise$1118  = \$1121 ;
+  assign \wr_pick$1114  = \$1115 ;
+  assign wrflag_shiftrot0_o_0 = \$1112 ;
+  assign \addr_en$1109  = \$1110 ;
+  assign \wp$1106  = \$1107 ;
+  assign \fus_cu_wr__go_i$103 [3] = \wr_pick_rise$1105 ;
+  assign \fus_cu_wr__go_i$103 [2] = \wr_pick_rise$1104 ;
+  assign \fus_cu_wr__go_i$103 [1] = \wr_pick_rise$1103 ;
+  assign \fus_cu_wr__go_i$103 [0] = \wr_pick_rise$1098 ;
+  assign \wr_pick_rise$1098  = \$1101 ;
+  assign \wr_pick$1094  = \$1095 ;
+  assign wrflag_mul0_o_0 = \$1092 ;
+  assign \addr_en$1089  = \$1090 ;
+  assign \wp$1086  = \$1087 ;
+  assign \fus_cu_wr__go_i$100 [3] = \wr_pick_rise$1085 ;
+  assign \fus_cu_wr__go_i$100 [2] = \wr_pick_rise$1084 ;
+  assign \fus_cu_wr__go_i$100 [1] = \wr_pick_rise$1083 ;
+  assign \fus_cu_wr__go_i$100 [0] = \wr_pick_rise$1078 ;
+  assign \wr_pick_rise$1078  = \$1081 ;
+  assign \wr_pick$1074  = \$1075 ;
+  assign wrflag_div0_o_0 = \$1072 ;
+  assign \addr_en$1069  = \$1070 ;
+  assign \wp$1066  = \$1067 ;
+  assign \fus_cu_wr__go_i$97 [1] = \wr_pick_rise$1065 ;
+  assign \fus_cu_wr__go_i$97 [2] = \wr_pick_rise$1064 ;
+  assign \fus_cu_wr__go_i$97 [3] = \wr_pick_rise$1063 ;
+  assign \fus_cu_wr__go_i$97 [4] = \wr_pick_rise$1062 ;
+  assign \fus_cu_wr__go_i$97 [5] = \wr_pick_rise$1061 ;
+  assign \fus_cu_wr__go_i$97 [0] = \wr_pick_rise$1056 ;
+  assign \wr_pick_rise$1056  = \$1059 ;
+  assign \wr_pick$1052  = \$1053 ;
+  assign wrflag_spr0_o_0 = \$1050 ;
+  assign \addr_en$1047  = \$1048 ;
+  assign \wp$1044  = \$1045 ;
+  assign \fus_cu_wr__go_i$94 [1] = \wr_pick_rise$1043 ;
+  assign \fus_cu_wr__go_i$94 [0] = \wr_pick_rise$1038 ;
+  assign \wr_pick_rise$1038  = \$1041 ;
+  assign \wr_pick$1034  = \$1035 ;
+  assign wrflag_logical0_o_0 = \$1032 ;
+  assign \addr_en$1029  = \$1030 ;
+  assign \wp$1026  = \$1027 ;
+  assign \fus_cu_wr__go_i$91 [6] = \wr_pick_rise$1025 ;
+  assign \fus_cu_wr__go_i$91 [5] = \wr_pick_rise$1024 ;
+  assign \fus_cu_wr__go_i$91 [4] = \wr_pick_rise$1023 ;
+  assign \fus_cu_wr__go_i$91 [3] = \wr_pick_rise$1022 ;
+  assign \fus_cu_wr__go_i$91 [2] = \wr_pick_rise$1021 ;
+  assign \fus_cu_wr__go_i$91 [1] = \wr_pick_rise$1020 ;
+  assign \fus_cu_wr__go_i$91 [0] = \wr_pick_rise$1015 ;
+  assign \wr_pick_rise$1015  = \$1018 ;
+  assign \wr_pick$1011  = \$1012 ;
+  assign wrflag_trap0_o_0 = \$1009 ;
+  assign \addr_en$1006  = \$1007 ;
+  assign \wp$1003  = \$1004 ;
+  assign \fus_cu_wr__go_i$88 [2] = \wr_pick_rise$1002 ;
+  assign \fus_cu_wr__go_i$88 [1] = \wr_pick_rise$1001 ;
+  assign \fus_cu_wr__go_i$88 [0] = \wr_pick_rise$996 ;
+  assign \wr_pick_rise$996  = \$999 ;
+  assign \wr_pick$992  = \$993 ;
+  assign wrflag_cr0_o_0 = \$990 ;
+  assign addr_en = \$988 ;
+  assign wp = \$986 ;
+  assign fus_cu_wr__go_i[4] = \wr_pick_rise$985 ;
+  assign fus_cu_wr__go_i[3] = \wr_pick_rise$984 ;
+  assign fus_cu_wr__go_i[2] = \wr_pick_rise$983 ;
+  assign fus_cu_wr__go_i[1] = \wr_pick_rise$982 ;
   assign fus_cu_wr__go_i[0] = wr_pick_rise;
-  assign wr_pick_rise = \$994 ;
-  assign wr_pick = \$990 ;
-  assign wrpick_INT_o_i[9] = \$988 ;
-  assign wrpick_INT_o_i[8] = \$986 ;
-  assign wrpick_INT_o_i[7] = \$984 ;
-  assign wrpick_INT_o_i[6] = \$982 ;
-  assign wrpick_INT_o_i[5] = \$980 ;
-  assign wrpick_INT_o_i[4] = \$978 ;
-  assign wrpick_INT_o_i[3] = \$976 ;
-  assign wrpick_INT_o_i[2] = \$974 ;
-  assign wrpick_INT_o_i[1] = \$972 ;
-  assign wrpick_INT_o_i[0] = \$970 ;
-  assign wrflag_alu0_o_0 = \$968 ;
-  assign spr_spr1__ren = \$966 ;
+  assign wr_pick_rise = \$980 ;
+  assign wr_pick = \$976 ;
+  assign wrpick_INT_o_i[9] = \$974 ;
+  assign wrpick_INT_o_i[8] = \$972 ;
+  assign wrpick_INT_o_i[7] = \$970 ;
+  assign wrpick_INT_o_i[6] = \$968 ;
+  assign wrpick_INT_o_i[5] = \$966 ;
+  assign wrpick_INT_o_i[4] = \$964 ;
+  assign wrpick_INT_o_i[3] = \$962 ;
+  assign wrpick_INT_o_i[2] = \$960 ;
+  assign wrpick_INT_o_i[1] = \$958 ;
+  assign wrpick_INT_o_i[0] = \$956 ;
+  assign wrflag_alu0_o_0 = \$954 ;
+  assign spr_spr1__ren = \$952 ;
   assign spr_spr1__addr = addr_en_SPR_spr1_spr0_0[3:0];
-  assign addr_en_SPR_spr1_spr0_0 = \$964 ;
-  assign rp_SPR_spr1_spr0_0 = \$962 ;
+  assign addr_en_SPR_spr1_spr0_0 = \$950 ;
+  assign rp_SPR_spr1_spr0_0 = \$948 ;
   assign rdpick_SPR_spr1_i = pick_SPR_spr1_spr0_0;
-  assign pick_SPR_spr1_spr0_0 = \$960 ;
+  assign pick_SPR_spr1_spr0_0 = \$946 ;
   assign rdflag_SPR_spr1_0 = core_spr1_ok;
-  assign fast_src1__ren = \$952 ;
-  assign fast_src1__addr = \$940 ;
-  assign addr_en_FAST_fast1_trap0_5 = \$938 ;
-  assign rp_FAST_fast1_trap0_5 = \$936 ;
-  assign pick_FAST_fast1_trap0_5 = \$934 ;
-  assign addr_en_FAST_fast1_trap0_4 = \$926 ;
-  assign rp_FAST_fast1_trap0_4 = \$924 ;
-  assign pick_FAST_fast1_trap0_4 = \$922 ;
-  assign addr_en_FAST_fast1_branch0_3 = \$914 ;
-  assign rp_FAST_fast1_branch0_3 = \$912 ;
-  assign pick_FAST_fast1_branch0_3 = \$910 ;
-  assign addr_en_FAST_fast1_spr0_2 = \$902 ;
-  assign rp_FAST_fast1_spr0_2 = \$900 ;
-  assign pick_FAST_fast1_spr0_2 = \$898 ;
-  assign addr_en_FAST_fast1_trap0_1 = \$890 ;
-  assign rp_FAST_fast1_trap0_1 = \$888 ;
-  assign pick_FAST_fast1_trap0_1 = \$886 ;
-  assign addr_en_FAST_fast1_branch0_0 = \$878 ;
-  assign rp_FAST_fast1_branch0_0 = \$876 ;
+  assign fast_src1__ren = \$938 ;
+  assign fast_src1__addr = \$926 ;
+  assign addr_en_FAST_fast1_trap0_5 = \$924 ;
+  assign rp_FAST_fast1_trap0_5 = \$922 ;
+  assign pick_FAST_fast1_trap0_5 = \$920 ;
+  assign addr_en_FAST_fast1_trap0_4 = \$912 ;
+  assign rp_FAST_fast1_trap0_4 = \$910 ;
+  assign pick_FAST_fast1_trap0_4 = \$908 ;
+  assign addr_en_FAST_fast1_branch0_3 = \$900 ;
+  assign rp_FAST_fast1_branch0_3 = \$898 ;
+  assign pick_FAST_fast1_branch0_3 = \$896 ;
+  assign addr_en_FAST_fast1_spr0_2 = \$888 ;
+  assign rp_FAST_fast1_spr0_2 = \$886 ;
+  assign pick_FAST_fast1_spr0_2 = \$884 ;
+  assign addr_en_FAST_fast1_trap0_1 = \$876 ;
+  assign rp_FAST_fast1_trap0_1 = \$874 ;
+  assign pick_FAST_fast1_trap0_1 = \$872 ;
+  assign addr_en_FAST_fast1_branch0_0 = \$864 ;
+  assign rp_FAST_fast1_branch0_0 = \$862 ;
   assign rdpick_FAST_fast1_i[5] = pick_FAST_fast1_trap0_5;
   assign rdpick_FAST_fast1_i[4] = pick_FAST_fast1_trap0_4;
   assign rdpick_FAST_fast1_i[3] = pick_FAST_fast1_branch0_3;
   assign rdpick_FAST_fast1_i[2] = pick_FAST_fast1_spr0_2;
   assign rdpick_FAST_fast1_i[1] = pick_FAST_fast1_trap0_1;
   assign rdpick_FAST_fast1_i[0] = pick_FAST_fast1_branch0_0;
-  assign pick_FAST_fast1_branch0_0 = \$874 ;
+  assign pick_FAST_fast1_branch0_0 = \$860 ;
   assign rdflag_FAST_fast1_2 = core_fast3_ok;
   assign rdflag_FAST_fast1_1 = core_fast2_ok;
   assign rdflag_FAST_fast1_0 = core_fast1_ok;
   assign cr_src3__ren = addr_en_CR_cr_c_cr0_0[7:0];
-  assign addr_en_CR_cr_c_cr0_0 = \$866 ;
-  assign rp_CR_cr_c_cr0_0 = \$860 ;
+  assign addr_en_CR_cr_c_cr0_0 = \$852 ;
+  assign rp_CR_cr_c_cr0_0 = \$846 ;
   assign rdpick_CR_cr_c_i = pick_CR_cr_c_cr0_0;
-  assign pick_CR_cr_c_cr0_0 = \$858 ;
+  assign pick_CR_cr_c_cr0_0 = \$844 ;
   assign rdflag_CR_cr_c_0 = \core_cr_in2_ok$2 ;
   assign cr_src2__ren = addr_en_CR_cr_b_cr0_0[7:0];
-  assign addr_en_CR_cr_b_cr0_0 = \$850 ;
-  assign rp_CR_cr_b_cr0_0 = \$844 ;
+  assign addr_en_CR_cr_b_cr0_0 = \$836 ;
+  assign rp_CR_cr_b_cr0_0 = \$830 ;
   assign rdpick_CR_cr_b_i = pick_CR_cr_b_cr0_0;
-  assign pick_CR_cr_b_cr0_0 = \$842 ;
+  assign pick_CR_cr_b_cr0_0 = \$828 ;
   assign rdflag_CR_cr_b_0 = core_cr_in2_ok;
-  assign cr_src1__ren = \$834 [7:0];
-  assign addr_en_CR_cr_a_branch0_1 = \$831 ;
-  assign rp_CR_cr_a_branch0_1 = \$825 ;
-  assign \fus_cu_rd__go_i$82 [1] = dp_FAST_fast1_branch0_3;
-  assign \fus_cu_rd__go_i$82 [0] = dp_FAST_fast1_branch0_0;
-  assign \fus_cu_rd__go_i$82 [2] = dp_CR_cr_a_branch0_1;
-  assign pick_CR_cr_a_branch0_1 = \$823 ;
-  assign addr_en_CR_cr_a_cr0_0 = \$815 ;
-  assign rp_CR_cr_a_cr0_0 = \$809 ;
+  assign cr_src1__ren = \$820 [7:0];
+  assign addr_en_CR_cr_a_branch0_1 = \$817 ;
+  assign rp_CR_cr_a_branch0_1 = \$811 ;
+  assign \fus_cu_rd__go_i$75 [1] = dp_FAST_fast1_branch0_3;
+  assign \fus_cu_rd__go_i$75 [0] = dp_FAST_fast1_branch0_0;
+  assign \fus_cu_rd__go_i$75 [2] = dp_CR_cr_a_branch0_1;
+  assign pick_CR_cr_a_branch0_1 = \$809 ;
+  assign addr_en_CR_cr_a_cr0_0 = \$801 ;
+  assign rp_CR_cr_a_cr0_0 = \$795 ;
   assign rdpick_CR_cr_a_i[1] = pick_CR_cr_a_branch0_1;
   assign rdpick_CR_cr_a_i[0] = pick_CR_cr_a_cr0_0;
-  assign pick_CR_cr_a_cr0_0 = \$807 ;
+  assign pick_CR_cr_a_cr0_0 = \$793 ;
   assign rdflag_CR_cr_a_0 = core_cr_in1_ok;
   assign cr_full_rd__ren = addr_en_CR_full_cr_cr0_0;
-  assign addr_en_CR_full_cr_cr0_0 = \$799 ;
-  assign rp_CR_full_cr_cr0_0 = \$797 ;
+  assign addr_en_CR_full_cr_cr0_0 = \$785 ;
+  assign rp_CR_full_cr_cr0_0 = \$783 ;
   assign rdpick_CR_full_cr_i = pick_CR_full_cr_cr0_0;
-  assign pick_CR_full_cr_cr0_0 = \$795 ;
+  assign pick_CR_full_cr_cr0_0 = \$781 ;
   assign rdflag_CR_full_cr_0 = core_core_cr_rd_ok;
   assign xer_src3__ren = addr_en_XER_xer_ov_spr0_0;
-  assign addr_en_XER_xer_ov_spr0_0 = \$787 ;
-  assign rp_XER_xer_ov_spr0_0 = \$785 ;
+  assign addr_en_XER_xer_ov_spr0_0 = \$773 ;
+  assign rp_XER_xer_ov_spr0_0 = \$771 ;
   assign rdpick_XER_xer_ov_i = pick_XER_xer_ov_spr0_0;
-  assign pick_XER_xer_ov_spr0_0 = \$783 ;
-  assign rdflag_XER_xer_ov_0 = \$775 ;
-  assign xer_src2__ren = \$763 ;
-  assign addr_en_XER_xer_ca_shiftrot0_2 = \$761 ;
-  assign rp_XER_xer_ca_shiftrot0_2 = \$759 ;
-  assign pick_XER_xer_ca_shiftrot0_2 = \$757 ;
-  assign addr_en_XER_xer_ca_spr0_1 = \$749 ;
-  assign rp_XER_xer_ca_spr0_1 = \$747 ;
-  assign pick_XER_xer_ca_spr0_1 = \$745 ;
-  assign addr_en_XER_xer_ca_alu0_0 = \$737 ;
-  assign rp_XER_xer_ca_alu0_0 = \$735 ;
+  assign pick_XER_xer_ov_spr0_0 = \$769 ;
+  assign rdflag_XER_xer_ov_0 = \$761 ;
+  assign xer_src2__ren = \$749 ;
+  assign addr_en_XER_xer_ca_shiftrot0_2 = \$747 ;
+  assign rp_XER_xer_ca_shiftrot0_2 = \$745 ;
+  assign pick_XER_xer_ca_shiftrot0_2 = \$743 ;
+  assign addr_en_XER_xer_ca_spr0_1 = \$735 ;
+  assign rp_XER_xer_ca_spr0_1 = \$733 ;
+  assign pick_XER_xer_ca_spr0_1 = \$731 ;
+  assign addr_en_XER_xer_ca_alu0_0 = \$723 ;
+  assign rp_XER_xer_ca_alu0_0 = \$721 ;
   assign rdpick_XER_xer_ca_i[2] = pick_XER_xer_ca_shiftrot0_2;
   assign rdpick_XER_xer_ca_i[1] = pick_XER_xer_ca_spr0_1;
   assign rdpick_XER_xer_ca_i[0] = pick_XER_xer_ca_alu0_0;
-  assign pick_XER_xer_ca_alu0_0 = \$733 ;
-  assign rdflag_XER_xer_ca_0 = \$725 ;
-  assign xer_src1__ren = \$707 ;
-  assign addr_en_XER_xer_so_shiftrot0_5 = \$705 ;
-  assign rp_XER_xer_so_shiftrot0_5 = \$703 ;
-  assign pick_XER_xer_so_shiftrot0_5 = \$701 ;
-  assign addr_en_XER_xer_so_mul0_4 = \$693 ;
-  assign rp_XER_xer_so_mul0_4 = \$691 ;
-  assign pick_XER_xer_so_mul0_4 = \$689 ;
-  assign addr_en_XER_xer_so_div0_3 = \$681 ;
-  assign rp_XER_xer_so_div0_3 = \$679 ;
-  assign pick_XER_xer_so_div0_3 = \$677 ;
-  assign addr_en_XER_xer_so_spr0_2 = \$669 ;
-  assign rp_XER_xer_so_spr0_2 = \$667 ;
-  assign pick_XER_xer_so_spr0_2 = \$665 ;
-  assign addr_en_XER_xer_so_logical0_1 = \$657 ;
-  assign rp_XER_xer_so_logical0_1 = \$655 ;
-  assign pick_XER_xer_so_logical0_1 = \$653 ;
-  assign addr_en_XER_xer_so_alu0_0 = \$645 ;
-  assign rp_XER_xer_so_alu0_0 = \$643 ;
+  assign pick_XER_xer_ca_alu0_0 = \$719 ;
+  assign rdflag_XER_xer_ca_0 = \$711 ;
+  assign xer_src1__ren = \$693 ;
+  assign addr_en_XER_xer_so_shiftrot0_5 = \$691 ;
+  assign rp_XER_xer_so_shiftrot0_5 = \$689 ;
+  assign pick_XER_xer_so_shiftrot0_5 = \$687 ;
+  assign addr_en_XER_xer_so_mul0_4 = \$679 ;
+  assign rp_XER_xer_so_mul0_4 = \$677 ;
+  assign pick_XER_xer_so_mul0_4 = \$675 ;
+  assign addr_en_XER_xer_so_div0_3 = \$667 ;
+  assign rp_XER_xer_so_div0_3 = \$665 ;
+  assign pick_XER_xer_so_div0_3 = \$663 ;
+  assign addr_en_XER_xer_so_spr0_2 = \$655 ;
+  assign rp_XER_xer_so_spr0_2 = \$653 ;
+  assign pick_XER_xer_so_spr0_2 = \$651 ;
+  assign addr_en_XER_xer_so_logical0_1 = \$643 ;
+  assign rp_XER_xer_so_logical0_1 = \$641 ;
+  assign pick_XER_xer_so_logical0_1 = \$639 ;
+  assign addr_en_XER_xer_so_alu0_0 = \$631 ;
+  assign rp_XER_xer_so_alu0_0 = \$629 ;
   assign rdpick_XER_xer_so_i[5] = pick_XER_xer_so_shiftrot0_5;
   assign rdpick_XER_xer_so_i[4] = pick_XER_xer_so_mul0_4;
   assign rdpick_XER_xer_so_i[3] = pick_XER_xer_so_div0_3;
   assign rdpick_XER_xer_so_i[2] = pick_XER_xer_so_spr0_2;
   assign rdpick_XER_xer_so_i[1] = pick_XER_xer_so_logical0_1;
   assign rdpick_XER_xer_so_i[0] = pick_XER_xer_so_alu0_0;
-  assign pick_XER_xer_so_alu0_0 = \$641 ;
-  assign rdflag_XER_xer_so_0 = \$633 ;
-  assign int_src1__ren = \$621 ;
-  assign int_src1__addr = \$619 [4:0];
-  assign addr_en_INT_rabc_ldst0_18 = \$582 ;
-  assign rp_INT_rabc_ldst0_18 = \$580 ;
-  assign pick_INT_rabc_ldst0_18 = \$578 ;
-  assign addr_en_INT_rabc_shiftrot0_17 = \$570 ;
-  assign rp_INT_rabc_shiftrot0_17 = \$568 ;
-  assign pick_INT_rabc_shiftrot0_17 = \$566 ;
-  assign addr_en_INT_rabc_mul0_16 = \$558 ;
-  assign rp_INT_rabc_mul0_16 = \$556 ;
-  assign pick_INT_rabc_mul0_16 = \$554 ;
-  assign addr_en_INT_rabc_div0_15 = \$546 ;
-  assign rp_INT_rabc_div0_15 = \$544 ;
-  assign pick_INT_rabc_div0_15 = \$542 ;
-  assign addr_en_INT_rabc_spr0_14 = \$534 ;
-  assign rp_INT_rabc_spr0_14 = \$532 ;
-  assign \fus_cu_rd__go_i$66 [1] = dp_SPR_spr1_spr0_0;
-  assign \fus_cu_rd__go_i$66 [2] = dp_FAST_fast1_spr0_2;
-  assign \fus_cu_rd__go_i$66 [4] = dp_XER_xer_ov_spr0_0;
-  assign \fus_cu_rd__go_i$66 [5] = dp_XER_xer_ca_spr0_1;
-  assign \fus_cu_rd__go_i$66 [3] = dp_XER_xer_so_spr0_2;
-  assign \fus_cu_rd__go_i$66 [0] = dp_INT_rabc_spr0_14;
-  assign pick_INT_rabc_spr0_14 = \$530 ;
-  assign addr_en_INT_rabc_logical0_13 = \$522 ;
-  assign rp_INT_rabc_logical0_13 = \$520 ;
-  assign pick_INT_rabc_logical0_13 = \$518 ;
-  assign addr_en_INT_rabc_trap0_12 = \$510 ;
-  assign rp_INT_rabc_trap0_12 = \$508 ;
-  assign pick_INT_rabc_trap0_12 = \$506 ;
-  assign addr_en_INT_rabc_cr0_11 = \$498 ;
-  assign rp_INT_rabc_cr0_11 = \$496 ;
-  assign pick_INT_rabc_cr0_11 = \$494 ;
-  assign addr_en_INT_rabc_alu0_10 = \$486 ;
-  assign rp_INT_rabc_alu0_10 = \$484 ;
-  assign pick_INT_rabc_alu0_10 = \$482 ;
-  assign addr_en_INT_rabc_ldst0_9 = \$474 ;
-  assign rp_INT_rabc_ldst0_9 = \$472 ;
-  assign pick_INT_rabc_ldst0_9 = \$470 ;
-  assign addr_en_INT_rabc_shiftrot0_8 = \$462 ;
-  assign rp_INT_rabc_shiftrot0_8 = \$460 ;
-  assign pick_INT_rabc_shiftrot0_8 = \$458 ;
-  assign addr_en_INT_rabc_ldst0_7 = \$450 ;
-  assign rp_INT_rabc_ldst0_7 = \$448 ;
-  assign \fus_cu_rd__go_i$59 [0] = dp_INT_rabc_ldst0_18;
-  assign \fus_cu_rd__go_i$59 [2] = dp_INT_rabc_ldst0_9;
-  assign \fus_cu_rd__go_i$59 [1] = dp_INT_rabc_ldst0_7;
-  assign pick_INT_rabc_ldst0_7 = \$446 ;
-  assign addr_en_INT_rabc_shiftrot0_6 = \$438 ;
-  assign rp_INT_rabc_shiftrot0_6 = \$436 ;
-  assign \fus_cu_rd__go_i$56 [4] = dp_XER_xer_ca_shiftrot0_2;
-  assign \fus_cu_rd__go_i$56 [3] = dp_XER_xer_so_shiftrot0_5;
-  assign \fus_cu_rd__go_i$56 [0] = dp_INT_rabc_shiftrot0_17;
-  assign \fus_cu_rd__go_i$56 [2] = dp_INT_rabc_shiftrot0_8;
-  assign \fus_cu_rd__go_i$56 [1] = dp_INT_rabc_shiftrot0_6;
-  assign pick_INT_rabc_shiftrot0_6 = \$434 ;
-  assign addr_en_INT_rabc_mul0_5 = \$426 ;
-  assign rp_INT_rabc_mul0_5 = \$424 ;
-  assign \fus_cu_rd__go_i$53 [2] = dp_XER_xer_so_mul0_4;
-  assign \fus_cu_rd__go_i$53 [0] = dp_INT_rabc_mul0_16;
-  assign \fus_cu_rd__go_i$53 [1] = dp_INT_rabc_mul0_5;
-  assign pick_INT_rabc_mul0_5 = \$422 ;
-  assign addr_en_INT_rabc_div0_4 = \$414 ;
-  assign rp_INT_rabc_div0_4 = \$412 ;
-  assign \fus_cu_rd__go_i$50 [2] = dp_XER_xer_so_div0_3;
-  assign \fus_cu_rd__go_i$50 [0] = dp_INT_rabc_div0_15;
-  assign \fus_cu_rd__go_i$50 [1] = dp_INT_rabc_div0_4;
-  assign pick_INT_rabc_div0_4 = \$410 ;
-  assign addr_en_INT_rabc_logical0_3 = \$402 ;
-  assign rp_INT_rabc_logical0_3 = \$400 ;
-  assign \fus_cu_rd__go_i$47 [2] = dp_XER_xer_so_logical0_1;
-  assign \fus_cu_rd__go_i$47 [0] = dp_INT_rabc_logical0_13;
-  assign \fus_cu_rd__go_i$47 [1] = dp_INT_rabc_logical0_3;
-  assign pick_INT_rabc_logical0_3 = \$398 ;
-  assign addr_en_INT_rabc_trap0_2 = \$390 ;
-  assign rp_INT_rabc_trap0_2 = \$388 ;
-  assign \fus_cu_rd__go_i$44 [4] = dp_FAST_fast1_trap0_5;
-  assign \fus_cu_rd__go_i$44 [3] = dp_FAST_fast1_trap0_4;
-  assign \fus_cu_rd__go_i$44 [2] = dp_FAST_fast1_trap0_1;
-  assign \fus_cu_rd__go_i$44 [0] = dp_INT_rabc_trap0_12;
-  assign \fus_cu_rd__go_i$44 [1] = dp_INT_rabc_trap0_2;
-  assign pick_INT_rabc_trap0_2 = \$386 ;
-  assign addr_en_INT_rabc_cr0_1 = \$378 ;
-  assign rp_INT_rabc_cr0_1 = \$376 ;
-  assign \fus_cu_rd__go_i$41 [5] = dp_CR_cr_c_cr0_0;
-  assign \fus_cu_rd__go_i$41 [4] = dp_CR_cr_b_cr0_0;
-  assign \fus_cu_rd__go_i$41 [3] = dp_CR_cr_a_cr0_0;
-  assign \fus_cu_rd__go_i$41 [2] = dp_CR_full_cr_cr0_0;
-  assign \fus_cu_rd__go_i$41 [0] = dp_INT_rabc_cr0_11;
-  assign \fus_cu_rd__go_i$41 [1] = dp_INT_rabc_cr0_1;
-  assign pick_INT_rabc_cr0_1 = \$374 ;
-  assign addr_en_INT_rabc_alu0_0 = \$366 ;
-  assign rp_INT_rabc_alu0_0 = \$364 ;
+  assign pick_XER_xer_so_alu0_0 = \$627 ;
+  assign rdflag_XER_xer_so_0 = \$619 ;
+  assign int_src1__ren = \$607 ;
+  assign int_src1__addr = \$605 [4:0];
+  assign addr_en_INT_rabc_ldst0_18 = \$568 ;
+  assign rp_INT_rabc_ldst0_18 = \$566 ;
+  assign pick_INT_rabc_ldst0_18 = \$564 ;
+  assign addr_en_INT_rabc_shiftrot0_17 = \$556 ;
+  assign rp_INT_rabc_shiftrot0_17 = \$554 ;
+  assign pick_INT_rabc_shiftrot0_17 = \$552 ;
+  assign addr_en_INT_rabc_mul0_16 = \$544 ;
+  assign rp_INT_rabc_mul0_16 = \$542 ;
+  assign pick_INT_rabc_mul0_16 = \$540 ;
+  assign addr_en_INT_rabc_div0_15 = \$532 ;
+  assign rp_INT_rabc_div0_15 = \$530 ;
+  assign pick_INT_rabc_div0_15 = \$528 ;
+  assign addr_en_INT_rabc_spr0_14 = \$520 ;
+  assign rp_INT_rabc_spr0_14 = \$518 ;
+  assign \fus_cu_rd__go_i$59 [1] = dp_SPR_spr1_spr0_0;
+  assign \fus_cu_rd__go_i$59 [2] = dp_FAST_fast1_spr0_2;
+  assign \fus_cu_rd__go_i$59 [4] = dp_XER_xer_ov_spr0_0;
+  assign \fus_cu_rd__go_i$59 [5] = dp_XER_xer_ca_spr0_1;
+  assign \fus_cu_rd__go_i$59 [3] = dp_XER_xer_so_spr0_2;
+  assign \fus_cu_rd__go_i$59 [0] = dp_INT_rabc_spr0_14;
+  assign pick_INT_rabc_spr0_14 = \$516 ;
+  assign addr_en_INT_rabc_logical0_13 = \$508 ;
+  assign rp_INT_rabc_logical0_13 = \$506 ;
+  assign pick_INT_rabc_logical0_13 = \$504 ;
+  assign addr_en_INT_rabc_trap0_12 = \$496 ;
+  assign rp_INT_rabc_trap0_12 = \$494 ;
+  assign pick_INT_rabc_trap0_12 = \$492 ;
+  assign addr_en_INT_rabc_cr0_11 = \$484 ;
+  assign rp_INT_rabc_cr0_11 = \$482 ;
+  assign pick_INT_rabc_cr0_11 = \$480 ;
+  assign addr_en_INT_rabc_alu0_10 = \$472 ;
+  assign rp_INT_rabc_alu0_10 = \$470 ;
+  assign pick_INT_rabc_alu0_10 = \$468 ;
+  assign addr_en_INT_rabc_ldst0_9 = \$460 ;
+  assign rp_INT_rabc_ldst0_9 = \$458 ;
+  assign pick_INT_rabc_ldst0_9 = \$456 ;
+  assign addr_en_INT_rabc_shiftrot0_8 = \$448 ;
+  assign rp_INT_rabc_shiftrot0_8 = \$446 ;
+  assign pick_INT_rabc_shiftrot0_8 = \$444 ;
+  assign addr_en_INT_rabc_ldst0_7 = \$436 ;
+  assign rp_INT_rabc_ldst0_7 = \$434 ;
+  assign \fus_cu_rd__go_i$52 [0] = dp_INT_rabc_ldst0_18;
+  assign \fus_cu_rd__go_i$52 [2] = dp_INT_rabc_ldst0_9;
+  assign \fus_cu_rd__go_i$52 [1] = dp_INT_rabc_ldst0_7;
+  assign pick_INT_rabc_ldst0_7 = \$432 ;
+  assign addr_en_INT_rabc_shiftrot0_6 = \$424 ;
+  assign rp_INT_rabc_shiftrot0_6 = \$422 ;
+  assign \fus_cu_rd__go_i$49 [4] = dp_XER_xer_ca_shiftrot0_2;
+  assign \fus_cu_rd__go_i$49 [3] = dp_XER_xer_so_shiftrot0_5;
+  assign \fus_cu_rd__go_i$49 [0] = dp_INT_rabc_shiftrot0_17;
+  assign \fus_cu_rd__go_i$49 [2] = dp_INT_rabc_shiftrot0_8;
+  assign \fus_cu_rd__go_i$49 [1] = dp_INT_rabc_shiftrot0_6;
+  assign pick_INT_rabc_shiftrot0_6 = \$420 ;
+  assign addr_en_INT_rabc_mul0_5 = \$412 ;
+  assign rp_INT_rabc_mul0_5 = \$410 ;
+  assign \fus_cu_rd__go_i$46 [2] = dp_XER_xer_so_mul0_4;
+  assign \fus_cu_rd__go_i$46 [0] = dp_INT_rabc_mul0_16;
+  assign \fus_cu_rd__go_i$46 [1] = dp_INT_rabc_mul0_5;
+  assign pick_INT_rabc_mul0_5 = \$408 ;
+  assign addr_en_INT_rabc_div0_4 = \$400 ;
+  assign rp_INT_rabc_div0_4 = \$398 ;
+  assign \fus_cu_rd__go_i$43 [2] = dp_XER_xer_so_div0_3;
+  assign \fus_cu_rd__go_i$43 [0] = dp_INT_rabc_div0_15;
+  assign \fus_cu_rd__go_i$43 [1] = dp_INT_rabc_div0_4;
+  assign pick_INT_rabc_div0_4 = \$396 ;
+  assign addr_en_INT_rabc_logical0_3 = \$388 ;
+  assign rp_INT_rabc_logical0_3 = \$386 ;
+  assign \fus_cu_rd__go_i$40 [2] = dp_XER_xer_so_logical0_1;
+  assign \fus_cu_rd__go_i$40 [0] = dp_INT_rabc_logical0_13;
+  assign \fus_cu_rd__go_i$40 [1] = dp_INT_rabc_logical0_3;
+  assign pick_INT_rabc_logical0_3 = \$384 ;
+  assign addr_en_INT_rabc_trap0_2 = \$376 ;
+  assign rp_INT_rabc_trap0_2 = \$374 ;
+  assign \fus_cu_rd__go_i$37 [4] = dp_FAST_fast1_trap0_5;
+  assign \fus_cu_rd__go_i$37 [3] = dp_FAST_fast1_trap0_4;
+  assign \fus_cu_rd__go_i$37 [2] = dp_FAST_fast1_trap0_1;
+  assign \fus_cu_rd__go_i$37 [0] = dp_INT_rabc_trap0_12;
+  assign \fus_cu_rd__go_i$37 [1] = dp_INT_rabc_trap0_2;
+  assign pick_INT_rabc_trap0_2 = \$372 ;
+  assign addr_en_INT_rabc_cr0_1 = \$364 ;
+  assign rp_INT_rabc_cr0_1 = \$362 ;
+  assign \fus_cu_rd__go_i$34 [5] = dp_CR_cr_c_cr0_0;
+  assign \fus_cu_rd__go_i$34 [4] = dp_CR_cr_b_cr0_0;
+  assign \fus_cu_rd__go_i$34 [3] = dp_CR_cr_a_cr0_0;
+  assign \fus_cu_rd__go_i$34 [2] = dp_CR_full_cr_cr0_0;
+  assign \fus_cu_rd__go_i$34 [0] = dp_INT_rabc_cr0_11;
+  assign \fus_cu_rd__go_i$34 [1] = dp_INT_rabc_cr0_1;
+  assign pick_INT_rabc_cr0_1 = \$360 ;
+  assign addr_en_INT_rabc_alu0_0 = \$352 ;
+  assign rp_INT_rabc_alu0_0 = \$350 ;
   assign fus_cu_rd__go_i[3] = dp_XER_xer_ca_alu0_0;
   assign fus_cu_rd__go_i[2] = dp_XER_xer_so_alu0_0;
   assign fus_cu_rd__go_i[0] = dp_INT_rabc_alu0_10;
@@ -53978,19 +53978,19 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   assign rdpick_INT_rabc_i[2] = pick_INT_rabc_trap0_2;
   assign rdpick_INT_rabc_i[1] = pick_INT_rabc_cr0_1;
   assign rdpick_INT_rabc_i[0] = pick_INT_rabc_alu0_0;
-  assign pick_INT_rabc_alu0_0 = \$362 ;
+  assign pick_INT_rabc_alu0_0 = \$348 ;
   assign rdflag_INT_rabc_2 = core_reg1_ok;
   assign rdflag_INT_rabc_1 = core_reg3_ok;
   assign rdflag_INT_rabc_0 = core_reg2_ok;
-  assign en_ldst0 = \$221 ;
-  assign en_shiftrot0 = \$217 ;
-  assign en_mul0 = \$213 ;
-  assign en_div0 = \$209 ;
-  assign en_spr0 = \$205 ;
-  assign en_logical0 = \$201 ;
-  assign en_trap0 = \$197 ;
-  assign en_branch0 = \$193 ;
-  assign en_cr0 = \$189 ;
+  assign en_ldst0 = \$207 ;
+  assign en_shiftrot0 = \$203 ;
+  assign en_mul0 = \$199 ;
+  assign en_div0 = \$195 ;
+  assign en_spr0 = \$191 ;
+  assign en_logical0 = \$187 ;
+  assign en_trap0 = \$183 ;
+  assign en_branch0 = \$179 ;
+  assign en_cr0 = \$175 ;
   assign fu_enable[9] = en_ldst0;
   assign fu_enable[8] = en_shiftrot0;
   assign fu_enable[7] = en_mul0;
@@ -54001,29 +54001,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c
   assign fu_enable[2] = en_branch0;
   assign fu_enable[1] = en_cr0;
   assign fu_enable[0] = en_alu0;
-  assign en_alu0 = \$185 ;
+  assign en_alu0 = \$171 ;
   assign dec_LDST_sv_a_nz = 1'h0;
   assign dec_LDST_bigendian = bigendian_i;
   assign dec_LDST_raw_opcode_in = raw_insn_i;
-  assign \sv_a_nz$184  = 1'h0;
+  assign \sv_a_nz$170  = 1'h0;
   assign dec_SHIFT_ROT_bigendian = bigendian_i;
   assign dec_SHIFT_ROT_raw_opcode_in = raw_insn_i;
-  assign \sv_a_nz$183  = 1'h0;
+  assign \sv_a_nz$169  = 1'h0;
   assign dec_MUL_bigendian = bigendian_i;
   assign dec_MUL_raw_opcode_in = raw_insn_i;
   assign dec_DIV_sv_a_nz = 1'h0;
   assign dec_DIV_bigendian = bigendian_i;
   assign dec_DIV_raw_opcode_in = raw_insn_i;
-  assign \sv_a_nz$182  = 1'h0;
+  assign \sv_a_nz$168  = 1'h0;
   assign dec_SPR_bigendian = bigendian_i;
   assign dec_SPR_raw_opcode_in = raw_insn_i;
   assign dec_LOGICAL_sv_a_nz = 1'h0;
   assign dec_LOGICAL_bigendian = bigendian_i;
   assign dec_LOGICAL_raw_opcode_in = raw_insn_i;
-  assign \sv_a_nz$181  = 1'h0;
+  assign \sv_a_nz$167  = 1'h0;
   assign dec_BRANCH_bigendian = bigendian_i;
   assign dec_BRANCH_raw_opcode_in = raw_insn_i;
-  assign \sv_a_nz$180  = 1'h0;
+  assign \sv_a_nz$166  = 1'h0;
   assign dec_CR_bigendian = bigendian_i;
   assign dec_CR_raw_opcode_in = raw_insn_i;
   assign dec_ALU_sv_a_nz = 1'h0;
@@ -84018,96 +84018,96 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.dec2" *)
 (* generator = "nMigen" *)
-module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl, cur_cur_dststep, cur_cur_srcstep, cur_cur_vl, cur_cur_maxvl, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fast3, fast3_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, fasto3, fasto3_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, sv_pred_sz, sv_pred_dz, sv_saturate, SV_Ptype, msr, cia, svstate, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, cur_eint);
+module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl, cur_cur_dststep, cur_cur_srcstep, cur_cur_vl, cur_cur_maxvl, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fast3, fast3_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, fasto3, fasto3_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, sv_pred_sz, sv_pred_dz, sv_saturate, SV_Ptype, msr, cia, svstate, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, exc_alignment, exc_instr_fault, exc_invalid, exc_badtree, exc_perm_error, exc_rc_error, exc_segment_fault, exc_happened, trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, cur_eint);
   reg \initial  = 0;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$100 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$102 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$104 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *)
-  wire \$106 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *)
-  wire \$108 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *)
-  wire \$110 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *)
-  wire \$112 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *)
-  wire \$114 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *)
-  wire \$116 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *)
-  wire \$118 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *)
-  wire \$120 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *)
-  wire \$28 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
-  wire \$30 ;
-  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
-  wire \$32 ;
+  wire \$11 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *)
-  wire \$34 ;
+  wire \$13 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$37 ;
+  wire \$16 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$39 ;
+  wire \$18 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$41 ;
+  wire \$20 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$43 ;
+  wire \$22 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$45 ;
+  wire \$24 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$47 ;
+  wire \$26 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$49 ;
+  wire \$28 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *)
-  wire \$51 ;
+  wire \$30 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *)
-  wire \$53 ;
+  wire \$32 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *)
-  wire \$55 ;
+  wire \$34 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *)
-  wire \$57 ;
+  wire \$36 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *)
-  wire \$59 ;
+  wire \$38 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *)
-  wire \$61 ;
+  wire \$40 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *)
-  wire \$63 ;
+  wire \$42 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *)
-  wire \$65 ;
+  wire \$44 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *)
-  wire \$67 ;
+  wire \$46 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *)
-  wire \$69 ;
+  wire \$48 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$71 ;
+  wire \$50 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$73 ;
+  wire \$52 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-  wire \$75 ;
+  wire \$54 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$77 ;
+  wire \$56 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$79 ;
+  wire \$58 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$81 ;
+  wire \$60 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *)
-  wire \$83 ;
+  wire \$62 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$90 ;
+  wire [6:0] \$69 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *)
+  wire \$7 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$92 ;
+  wire [6:0] \$71 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$94 ;
+  wire [6:0] \$73 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
+  wire [6:0] \$75 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
+  wire [6:0] \$77 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$96 ;
+  wire [6:0] \$79 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \$98 ;
+  wire [6:0] \$81 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
+  wire [6:0] \$83 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *)
+  wire \$85 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *)
+  wire \$87 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *)
+  wire \$89 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
+  wire \$9 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *)
+  wire \$91 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *)
+  wire \$93 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *)
+  wire \$95 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *)
+  wire \$97 ;
+  (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *)
+  wire \$99 ;
   (* enum_base_type = "SVPtype" *)
   (* enum_value_00 = "NONE" *)
   (* enum_value_01 = "P1" *)
@@ -84180,21 +84180,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *)
   input [63:0] cur_pc;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal ;
+  wire dec2_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$12 ;
+  wire dec2_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$13 ;
+  wire dec2_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$14 ;
+  wire dec2_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$15 ;
+  wire dec2_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$16 ;
+  wire dec2_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$17 ;
+  wire dec2_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$18 ;
+  wire dec2_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *)
   wire [4:0] dec_BA;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *)
@@ -84836,29 +84836,29 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   output ea_ok;
   reg ea_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal ;
-  reg \exc_$signal ;
+  output exc_alignment;
+  reg exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$3 ;
-  reg \exc_$signal$3 ;
+  output exc_badtree;
+  reg exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$4 ;
-  reg \exc_$signal$4 ;
+  output exc_happened;
+  reg exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$5 ;
-  reg \exc_$signal$5 ;
+  output exc_instr_fault;
+  reg exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$6 ;
-  reg \exc_$signal$6 ;
+  output exc_invalid;
+  reg exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$7 ;
-  reg \exc_$signal$7 ;
+  output exc_perm_error;
+  reg exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$8 ;
-  reg \exc_$signal$8 ;
+  output exc_rc_error;
+  reg exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_$signal$9 ;
-  reg \exc_$signal$9 ;
+  output exc_segment_fault;
+  reg exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1299" *)
   wire ext_irq_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -84931,17 +84931,17 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *)
   wire [31:0] insn_in;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *)
-  wire [31:0] \insn_in$36 ;
+  wire [31:0] \insn_in$15 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:111" *)
-  wire [31:0] \insn_in$85 ;
+  wire [31:0] \insn_in$64 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:223" *)
-  wire [31:0] \insn_in$86 ;
+  wire [31:0] \insn_in$65 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:332" *)
-  wire [31:0] \insn_in$87 ;
+  wire [31:0] \insn_in$66 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:374" *)
-  wire [31:0] \insn_in$88 ;
+  wire [31:0] \insn_in$67 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:442" *)
-  wire [31:0] \insn_in$89 ;
+  wire [31:0] \insn_in$68 ;
   (* enum_base_type = "MicrOp" *)
   (* enum_value_0000000 = "OP_ILLEGAL" *)
   (* enum_value_0000001 = "OP_NOP" *)
@@ -85355,11 +85355,11 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [6:0] tmp_cr_in2;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \tmp_cr_in2$19 ;
+  wire [6:0] \tmp_cr_in2$5 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire tmp_cr_in2_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \tmp_cr_in2_ok$20 ;
+  wire \tmp_cr_in2_ok$6 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [6:0] tmp_cr_out;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -85671,21 +85671,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire tmp_tmp_cr_wr_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal ;
+  wire tmp_tmp_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$21 ;
+  wire tmp_tmp_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$22 ;
+  wire tmp_tmp_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$23 ;
+  wire tmp_tmp_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$24 ;
+  wire tmp_tmp_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$25 ;
+  wire tmp_tmp_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$26 ;
+  wire tmp_tmp_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \tmp_tmp_exc_$signal$27 ;
+  wire tmp_tmp_exc_segment_fault;
   (* enum_base_type = "Function" *)
   (* enum_value_000000000000000 = "NONE" *)
   (* enum_value_000000000000010 = "ALU" *)
@@ -85827,50 +85827,50 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *)
   output xer_out;
   reg xer_out;
-  assign \$100  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_b;
-  assign \$102  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_o;
-  assign \$104  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_out_cr_bitfield;
-  assign \$106  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) 7'h2e;
-  assign \$108  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) 7'h0a;
-  assign \$110  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) 7'h31;
-  assign \$112  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) 7'h3f;
-  assign \$114  = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *) cur_msr[15];
-  assign \$116  = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *) cur_msr[15];
-  assign \$118  = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *) cur_msr[14];
-  assign \$120  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *) 7'h00;
-  assign \$28  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *) 7'h3f;
-  assign \$30  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) 7'h49;
-  assign \$32  = \$28  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) \$30 ;
-  assign \$34  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) 7'h46;
-  assign \$37  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400;
-  assign \$39  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$37 ;
-  assign \$41  = \$39  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr;
-  assign \$43  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800;
-  assign \$45  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$43 ;
-  assign \$47  = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr;
-  assign \$49  = \$45  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$47 ;
-  assign \$51  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31;
-  assign \$53  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e;
-  assign \$55  = \$51  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$53 ;
-  assign \$57  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12;
-  assign \$59  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13;
-  assign \$61  = \$57  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$59 ;
-  assign \$63  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0;
-  assign \$65  = \$61  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$63 ;
-  assign \$67  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30;
-  assign \$69  = \$65  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$67 ;
-  assign \$71  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400;
-  assign \$73  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$71 ;
-  assign \$75  = \$73  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr;
-  assign \$77  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800;
-  assign \$79  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$77 ;
-  assign \$81  = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr;
-  assign \$83  = \$79  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$81 ;
-  assign \$90  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_a_reg_a;
-  assign \$92  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_c_reg_c;
-  assign \$94  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o_reg_o;
-  assign \$96  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o2_reg_o2;
-  assign \$98  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield;
+  assign \$9  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) 7'h49;
+  assign \$99  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *) 7'h00;
+  assign \$11  = \$7  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) \$9 ;
+  assign \$13  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) 7'h46;
+  assign \$16  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400;
+  assign \$18  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$16 ;
+  assign \$20  = \$18  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr;
+  assign \$22  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800;
+  assign \$24  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$22 ;
+  assign \$26  = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr;
+  assign \$28  = \$24  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$26 ;
+  assign \$30  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31;
+  assign \$32  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e;
+  assign \$34  = \$30  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$32 ;
+  assign \$36  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12;
+  assign \$38  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13;
+  assign \$40  = \$36  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$38 ;
+  assign \$42  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0;
+  assign \$44  = \$40  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$42 ;
+  assign \$46  = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30;
+  assign \$48  = \$44  | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$46 ;
+  assign \$50  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400;
+  assign \$52  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$50 ;
+  assign \$54  = \$52  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr;
+  assign \$56  = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800;
+  assign \$58  = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$56 ;
+  assign \$60  = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr;
+  assign \$62  = \$58  & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$60 ;
+  assign \$69  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_a_reg_a;
+  assign \$71  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_c_reg_c;
+  assign \$73  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o_reg_o;
+  assign \$75  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o2_reg_o2;
+  assign \$77  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield;
+  assign \$7  = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *) 7'h3f;
+  assign \$79  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_b;
+  assign \$81  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_o;
+  assign \$83  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_out_cr_bitfield;
+  assign \$85  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) 7'h2e;
+  assign \$87  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) 7'h0a;
+  assign \$89  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) 7'h31;
+  assign \$91  = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) 7'h3f;
+  assign \$93  = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *) cur_msr[15];
+  assign \$95  = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *) cur_msr[15];
+  assign \$97  = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *) cur_msr[14];
   \dec$171  dec (
     .BA(dec_BA),
     .BB(dec_BB),
@@ -85953,7 +85953,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     .reg_c_ok(dec_c_reg_c_ok),
     .sel_in(dec_c_sel_in)
   );
-  dec_cr_in \dec_cr_in$10  (
+  dec_cr_in \dec_cr_in$3  (
     .BA(dec_BA),
     .BB(dec_BB),
     .BC(dec_BC),
@@ -85973,7 +85973,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     .internal_op(dec_internal_op),
     .sel_in(dec_cr_in_sel_in)
   );
-  dec_cr_out \dec_cr_out$11  (
+  dec_cr_out \dec_cr_out$4  (
     .FXM(dec_FXM),
     .XL_BT(dec_XL_BT),
     .X_BF(dec_X_BF),
@@ -86030,7 +86030,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     (* full_case = 32'd1 *)
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-    casez ({ \$83 , \$75  })
+    casez ({ \$62 , \$54  })
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */
       2'b?1:
           tmp_tmp_fn_unit = 15'h0000;
@@ -86056,13 +86056,13 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     tmp_xer_in = 3'h0;
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *)
-    casez (\$106 )
+    casez (\$85 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" */
       1'h1:
           tmp_xer_in = 3'h7;
     endcase
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *)
-    casez (\$108 )
+    casez (\$87 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" */
       1'h1:
           tmp_xer_in = 3'h1;
@@ -86072,7 +86072,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     tmp_xer_out = 1'h0;
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *)
-    casez (\$110 )
+    casez (\$89 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" */
       1'h1:
           tmp_xer_out = 1'h1;
@@ -86082,7 +86082,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     tmp_tmp_trapaddr = 13'h0000;
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *)
-    casez (\$112 )
+    casez (\$91 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" */
       1'h1:
           tmp_tmp_trapaddr = 13'h0070;
@@ -86116,7 +86116,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     tmp_tmp_insn_type = dec_internal_op;
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
-    casez ({ \$49 , \$41  })
+    casez ({ \$28 , \$20  })
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */
       2'b?1:
           tmp_tmp_insn_type = 7'h00;
@@ -86129,16 +86129,16 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
     if (\initial ) begin end
     (* full_case = 32'd1 *)
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" *)
-    casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal  })
+    casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, dec2_exc_happened })
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" */
       5'b????1:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" *)
-          casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12  })
+          casez ({ dec2_exc_instr_fault, dec2_exc_alignment })
             /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" */
             2'b?1:
               begin
-                { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+                { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                 insn = dec_opcode_in;
                 insn_type = 7'h3f;
                 fn_unit = 15'h0080;
@@ -86152,11 +86152,11 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
             2'b1?:
                 (* full_case = 32'd1 *)
                 (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" *)
-                casez (\dec2_exc_$signal$14 )
+                casez (dec2_exc_segment_fault)
                   /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" */
                   1'h1:
                     begin
-                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                       insn = dec_opcode_in;
                       insn_type = 7'h3f;
                       fn_unit = 15'h0080;
@@ -86169,13 +86169,13 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
                   /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1318" */
                   default:
                     begin
-                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                       insn = dec_opcode_in;
                       insn_type = 7'h3f;
                       fn_unit = 15'h0080;
                       trapaddr = 13'h0040;
                       traptype = 8'h40;
-                      { \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal  } = { \dec2_exc_$signal , \dec2_exc_$signal$14 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal$15 , \dec2_exc_$signal$13 , \dec2_exc_$signal$12  };
+                      { exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment } = { dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment };
                       msr = cur_msr;
                       cia = cur_pc;
                       svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
@@ -86185,11 +86185,11 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
             default:
                 (* full_case = 32'd1 *)
                 (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" *)
-                casez (\dec2_exc_$signal$14 )
+                casez (dec2_exc_segment_fault)
                   /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" */
                   1'h1:
                     begin
-                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                       insn = dec_opcode_in;
                       insn_type = 7'h3f;
                       fn_unit = 15'h0080;
@@ -86202,7 +86202,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
                   /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1324" */
                   default:
                     begin
-                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+                      { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                       insn = dec_opcode_in;
                       insn_type = 7'h3f;
                       fn_unit = 15'h0080;
@@ -86217,7 +86217,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1328" */
       5'b???1?:
         begin
-          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
           insn = dec_opcode_in;
           insn_type = 7'h3f;
           fn_unit = 15'h0080;
@@ -86230,7 +86230,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1332" */
       5'b??1??:
         begin
-          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
           insn = dec_opcode_in;
           insn_type = 7'h3f;
           fn_unit = 15'h0080;
@@ -86243,7 +86243,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1336" */
       5'b?1???:
         begin
-          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
           insn = dec_opcode_in;
           insn_type = 7'h3f;
           fn_unit = 15'h0080;
@@ -86256,7 +86256,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1343" */
       5'h1?:
         begin
-          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
           insn = dec_opcode_in;
           insn_type = 7'h3f;
           fn_unit = 15'h0080;
@@ -86268,10 +86268,10 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
         end
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1348" */
       default:
-          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_svstate, tmp_tmp_cia, tmp_tmp_msr, tmp_tmp__SV_Ptype, tmp_tmp__sv_saturate, tmp_tmp__sv_pred_dz, tmp_tmp__sv_pred_sz, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto3_ok, tmp_fasto3, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast3_ok, tmp_fast3, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode };
+          { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, tmp_tmp_exc_happened, tmp_tmp_exc_segment_fault, tmp_tmp_exc_rc_error, tmp_tmp_exc_perm_error, tmp_tmp_exc_badtree, tmp_tmp_exc_invalid, tmp_tmp_exc_instr_fault, tmp_tmp_exc_alignment, tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_svstate, tmp_tmp_cia, tmp_tmp_msr, tmp_tmp__SV_Ptype, tmp_tmp__sv_saturate, tmp_tmp__sv_pred_dz, tmp_tmp__sv_pred_sz, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$6 , \tmp_cr_in2$5 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto3_ok, tmp_fasto3, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast3_ok, tmp_fast3, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode };
     endcase
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
-    casez (\$32 )
+    casez (\$11 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" */
       1'h1:
         begin
@@ -86284,7 +86284,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
         end
     endcase
     (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *)
-    casez (\$34 )
+    casez (\$13 )
       /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" */
       1'h1:
         begin
@@ -86300,14 +86300,14 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
         asmcode = dec_asmcode;
     end
   end
-  assign \dec2_exc_$signal  = 1'h0;
-  assign \dec2_exc_$signal$12  = 1'h0;
-  assign \dec2_exc_$signal$13  = 1'h0;
-  assign \dec2_exc_$signal$14  = 1'h0;
-  assign \dec2_exc_$signal$15  = 1'h0;
-  assign \dec2_exc_$signal$16  = 1'h0;
-  assign \dec2_exc_$signal$17  = 1'h0;
-  assign \dec2_exc_$signal$18  = 1'h0;
+  assign dec2_exc_happened = 1'h0;
+  assign dec2_exc_alignment = 1'h0;
+  assign dec2_exc_instr_fault = 1'h0;
+  assign dec2_exc_segment_fault = 1'h0;
+  assign dec2_exc_invalid = 1'h0;
+  assign dec2_exc_badtree = 1'h0;
+  assign dec2_exc_perm_error = 1'h0;
+  assign dec2_exc_rc_error = 1'h0;
   assign tmp_asmcode = 8'h00;
   assign tmp_fast3 = 3'h0;
   assign tmp_fast3_ok = 1'h0;
@@ -86316,19 +86316,19 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   assign tmp_tmp__sv_saturate = 2'h0;
   assign tmp_tmp__SV_Ptype = 2'h0;
   assign tmp_tmp_traptype = 8'h00;
-  assign \tmp_tmp_exc_$signal  = 1'h0;
-  assign \tmp_tmp_exc_$signal$21  = 1'h0;
-  assign \tmp_tmp_exc_$signal$22  = 1'h0;
-  assign \tmp_tmp_exc_$signal$23  = 1'h0;
-  assign \tmp_tmp_exc_$signal$24  = 1'h0;
-  assign \tmp_tmp_exc_$signal$25  = 1'h0;
-  assign \tmp_tmp_exc_$signal$26  = 1'h0;
-  assign \tmp_tmp_exc_$signal$27  = 1'h0;
+  assign tmp_tmp_exc_alignment = 1'h0;
+  assign tmp_tmp_exc_instr_fault = 1'h0;
+  assign tmp_tmp_exc_invalid = 1'h0;
+  assign tmp_tmp_exc_badtree = 1'h0;
+  assign tmp_tmp_exc_perm_error = 1'h0;
+  assign tmp_tmp_exc_rc_error = 1'h0;
+  assign tmp_tmp_exc_segment_fault = 1'h0;
+  assign tmp_tmp_exc_happened = 1'h0;
   assign sv_a_nz = 1'h0;
-  assign illeg_ok = \$120 ;
-  assign priv_ok = \$118 ;
-  assign dec_irq_ok = \$116 ;
-  assign ext_irq_ok = \$114 ;
+  assign illeg_ok = \$99 ;
+  assign priv_ok = \$97 ;
+  assign dec_irq_ok = \$95 ;
+  assign ext_irq_ok = \$93 ;
   assign { tmp_fasto3_ok, tmp_fasto3 } = { dec_o2_fast_o3_ok, dec_o2_fast_o3 };
   assign { tmp_fasto2_ok, tmp_fasto2 } = { dec_o2_fast_o2_ok, dec_o2_fast_o2 };
   assign { tmp_fasto1_ok, tmp_fasto1 } = { dec_o_fast_o_ok, dec_o_fast_o };
@@ -86337,23 +86337,23 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   assign { tmp_spro_ok, tmp_spro } = { dec_o_spr_o_ok, dec_o_spr_o };
   assign { tmp_spr1_ok, tmp_spr1 } = { dec_a_spr_a_ok, dec_a_spr_a };
   assign tmp_cr_out_ok = dec_cr_out_cr_bitfield_ok;
-  assign tmp_cr_out = \$104 ;
-  assign \tmp_cr_in2_ok$20  = dec_cr_in_cr_bitfield_o_ok;
-  assign \tmp_cr_in2$19  = \$102 ;
+  assign tmp_cr_out = \$83 ;
+  assign \tmp_cr_in2_ok$6  = dec_cr_in_cr_bitfield_o_ok;
+  assign \tmp_cr_in2$5  = \$81 ;
   assign tmp_cr_in2_ok = dec_cr_in_cr_bitfield_b_ok;
-  assign tmp_cr_in2 = \$100 ;
+  assign tmp_cr_in2 = \$79 ;
   assign tmp_cr_in1_ok = dec_cr_in_cr_bitfield_ok;
-  assign tmp_cr_in1 = \$98 ;
+  assign tmp_cr_in1 = \$77 ;
   assign tmp_ea_ok = dec_o2_reg_o2_ok;
-  assign tmp_ea = \$96 ;
+  assign tmp_ea = \$75 ;
   assign tmp_rego_ok = dec_o_reg_o_ok;
-  assign tmp_rego = \$94 ;
+  assign tmp_rego = \$73 ;
   assign tmp_reg3_ok = dec_c_reg_c_ok;
-  assign tmp_reg3 = \$92 ;
+  assign tmp_reg3 = \$71 ;
   assign tmp_reg2_ok = dec_b_reg_b_ok;
   assign tmp_reg2 = dec_b_reg_b;
   assign tmp_reg1_ok = dec_a_reg_a_ok;
-  assign tmp_reg1 = \$90 ;
+  assign tmp_reg1 = \$69 ;
   assign dec_o2_lk = tmp_tmp_lk;
   assign sel_in = dec_out_sel;
   assign dec_o_sel_in = dec_out_sel;
@@ -86365,28 +86365,28 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl,
   assign dec_cr_out_rc_in = dec_rc_rc;
   assign dec_cr_out_sel_in = dec_cr_out;
   assign dec_cr_in_sel_in = dec_cr_in;
-  assign \insn_in$89  = dec_opcode_in;
-  assign \insn_in$88  = dec_opcode_in;
-  assign \insn_in$87  = dec_opcode_in;
+  assign \insn_in$68  = dec_opcode_in;
+  assign \insn_in$67  = dec_opcode_in;
+  assign \insn_in$66  = dec_opcode_in;
   assign dec_cr_out_insn_in = dec_opcode_in;
   assign dec_cr_in_insn_in = dec_opcode_in;
-  assign \insn_in$86  = dec_opcode_in;
-  assign \insn_in$85  = dec_opcode_in;
+  assign \insn_in$65  = dec_opcode_in;
+  assign \insn_in$64  = dec_opcode_in;
   assign tmp_tmp_insn = dec_opcode_in;
   assign dec_a_sv_nz = 1'h0;
   assign tmp_tmp_is_32bit = dec_is_32b;
   assign tmp_tmp_input_carry = dec_cry_in;
   assign { tmp_tmp_oe_ok, tmp_tmp_oe } = { dec_oe_oe_ok, dec_oe_oe };
   assign { tmp_tmp_rc_ok, tmp_tmp_rc } = { dec_rc_rc_ok, dec_rc_rc };
-  assign is_mmu_spr = \$69 ;
-  assign is_spr_mv = \$55 ;
+  assign is_mmu_spr = \$48 ;
+  assign is_spr_mv = \$34 ;
   assign spr = { dec_SPR[4:0], dec_SPR[9:5] };
   assign tmp_tmp_svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
   assign tmp_tmp_cia = cur_pc;
   assign tmp_tmp_msr = cur_msr;
   assign dec_oe_sel_in = dec_rc_sel;
   assign dec_rc_sel_in = dec_rc_sel;
-  assign \insn_in$36  = dec_opcode_in;
+  assign \insn_in$15  = dec_opcode_in;
   assign insn_in = dec_opcode_in;
 endmodule
 
@@ -143332,7 +143332,7 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.fus" *)
 (* generator = "nMigen" *)
-module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \exc_o_$signal , oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , \ldst_port0_exc_$signal$158 , \ldst_port0_exc_$signal$159 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
+module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
   input coresync_clk;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
@@ -143574,7 +143574,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   output [63:0] ea;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_o_$signal ;
+  output exc_o_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   output fast1_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -143600,21 +143600,21 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   output [3:0] ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal ;
+  input ldst_port0_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$153 ;
+  input ldst_port0_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$154 ;
+  input ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$155 ;
+  input ldst_port0_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$156 ;
+  input ldst_port0_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$157 ;
+  input ldst_port0_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$158 ;
+  input ldst_port0_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$159 ;
+  input ldst_port0_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   output ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -145290,20 +145290,20 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \
     .cu_wr__go_i(\cu_wr__go_i$103 ),
     .cu_wr__rel_o(\cu_wr__rel_o$102 ),
     .ea(ea),
-    .\exc_o_$signal (\exc_o_$signal ),
+    .exc_o_happened(exc_o_happened),
     .ldst_port0_addr_i(ldst_port0_addr_i),
     .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok),
     .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o),
     .ldst_port0_busy_o(ldst_port0_busy_o),
     .ldst_port0_data_len(ldst_port0_data_len),
-    .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ),
-    .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$153 ),
-    .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$154 ),
-    .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$155 ),
-    .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$156 ),
-    .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$157 ),
-    .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$158 ),
-    .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$159 ),
+    .ldst_port0_exc_alignment(ldst_port0_exc_alignment),
+    .ldst_port0_exc_badtree(ldst_port0_exc_badtree),
+    .ldst_port0_exc_happened(ldst_port0_exc_happened),
+    .ldst_port0_exc_instr_fault(ldst_port0_exc_instr_fault),
+    .ldst_port0_exc_invalid(ldst_port0_exc_invalid),
+    .ldst_port0_exc_perm_error(ldst_port0_exc_perm_error),
+    .ldst_port0_exc_rc_error(ldst_port0_exc_rc_error),
+    .ldst_port0_exc_segment_fault(ldst_port0_exc_segment_fault),
     .ldst_port0_is_ld_i(ldst_port0_is_ld_i),
     .ldst_port0_is_st_i(ldst_port0_is_st_i),
     .ldst_port0_ld_data_o(ldst_port0_ld_data_o),
@@ -150745,7 +150745,7 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.l0" *)
 (* generator = "nMigen" *)
-module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
+module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
   input coresync_clk;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
@@ -150779,21 +150779,21 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   input [3:0] ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal ;
+  output ldst_port0_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$1 ;
+  output ldst_port0_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$2 ;
+  output ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$3 ;
+  output ldst_port0_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$4 ;
+  output ldst_port0_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$5 ;
+  output ldst_port0_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$6 ;
+  output ldst_port0_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$7 ;
+  output ldst_port0_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   input ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -150819,7 +150819,7 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   wire [3:0] pimem_ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \pimem_ldst_port0_exc_$signal ;
+  wire pimem_ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   wire pimem_ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -150856,37 +150856,37 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
     .ldst_port0_addr_i(ldst_port0_addr_i),
-    .\ldst_port0_addr_i$12 (pimem_ldst_port0_addr_i),
+    .\ldst_port0_addr_i$5 (pimem_ldst_port0_addr_i),
     .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok),
-    .\ldst_port0_addr_i_ok$13 (pimem_ldst_port0_addr_i_ok),
+    .\ldst_port0_addr_i_ok$6 (pimem_ldst_port0_addr_i_ok),
     .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o),
-    .\ldst_port0_addr_ok_o$14 (pimem_ldst_port0_addr_ok_o),
+    .\ldst_port0_addr_ok_o$7 (pimem_ldst_port0_addr_ok_o),
     .ldst_port0_busy_o(ldst_port0_busy_o),
-    .\ldst_port0_busy_o$10 (pimem_ldst_port0_busy_o),
+    .\ldst_port0_busy_o$3 (pimem_ldst_port0_busy_o),
     .ldst_port0_data_len(ldst_port0_data_len),
-    .\ldst_port0_data_len$11 (pimem_ldst_port0_data_len),
-    .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ),
-    .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$1 ),
-    .\ldst_port0_exc_$signal$19 (\pimem_ldst_port0_exc_$signal ),
-    .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$2 ),
-    .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$3 ),
-    .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$4 ),
-    .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$5 ),
-    .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$6 ),
-    .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$7 ),
+    .\ldst_port0_data_len$4 (pimem_ldst_port0_data_len),
+    .ldst_port0_exc_alignment(ldst_port0_exc_alignment),
+    .ldst_port0_exc_badtree(ldst_port0_exc_badtree),
+    .ldst_port0_exc_happened(ldst_port0_exc_happened),
+    .\ldst_port0_exc_happened$12 (pimem_ldst_port0_exc_happened),
+    .ldst_port0_exc_instr_fault(ldst_port0_exc_instr_fault),
+    .ldst_port0_exc_invalid(ldst_port0_exc_invalid),
+    .ldst_port0_exc_perm_error(ldst_port0_exc_perm_error),
+    .ldst_port0_exc_rc_error(ldst_port0_exc_rc_error),
+    .ldst_port0_exc_segment_fault(ldst_port0_exc_segment_fault),
     .ldst_port0_is_ld_i(ldst_port0_is_ld_i),
-    .\ldst_port0_is_ld_i$8 (pimem_ldst_port0_is_ld_i),
+    .\ldst_port0_is_ld_i$1 (pimem_ldst_port0_is_ld_i),
     .ldst_port0_is_st_i(ldst_port0_is_st_i),
-    .\ldst_port0_is_st_i$9 (pimem_ldst_port0_is_st_i),
+    .\ldst_port0_is_st_i$2 (pimem_ldst_port0_is_st_i),
     .ldst_port0_ld_data_o(ldst_port0_ld_data_o),
-    .\ldst_port0_ld_data_o$15 (pimem_ldst_port0_ld_data_o),
+    .\ldst_port0_ld_data_o$8 (pimem_ldst_port0_ld_data_o),
     .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok),
-    .\ldst_port0_ld_data_o_ok$16 (pimem_ldst_port0_ld_data_o_ok),
+    .\ldst_port0_ld_data_o_ok$9 (pimem_ldst_port0_ld_data_o_ok),
     .ldst_port0_msr_pr(ldst_port0_msr_pr),
     .ldst_port0_st_data_i(ldst_port0_st_data_i),
-    .\ldst_port0_st_data_i$18 (pimem_ldst_port0_st_data_i),
+    .\ldst_port0_st_data_i$11 (pimem_ldst_port0_st_data_i),
     .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok),
-    .\ldst_port0_st_data_i_ok$17 (pimem_ldst_port0_st_data_i_ok)
+    .\ldst_port0_st_data_i_ok$10 (pimem_ldst_port0_st_data_i_ok)
   );
   lsmem lsmem (
     .coresync_clk(coresync_clk),
@@ -150919,7 +150919,7 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_
     .ldst_port0_addr_ok_o(pimem_ldst_port0_addr_ok_o),
     .ldst_port0_busy_o(pimem_ldst_port0_busy_o),
     .ldst_port0_data_len(pimem_ldst_port0_data_len),
-    .\ldst_port0_exc_$signal (\pimem_ldst_port0_exc_$signal ),
+    .ldst_port0_exc_happened(pimem_ldst_port0_exc_happened),
     .ldst_port0_is_ld_i(pimem_ldst_port0_is_ld_i),
     .ldst_port0_is_st_i(pimem_ldst_port0_is_st_i),
     .ldst_port0_ld_data_o(pimem_ldst_port0_ld_data_o),
@@ -150936,35 +150936,35 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_
     .x_st_i(pimem_x_st_i),
     .x_valid_i(pimem_x_valid_i)
   );
-  assign \pimem_ldst_port0_exc_$signal  = 1'h0;
+  assign pimem_ldst_port0_exc_happened = 1'h0;
 endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.l0.l0" *)
 (* generator = "nMigen" *)
-module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$8 , \ldst_port0_is_st_i$9 , \ldst_port0_busy_o$10 , \ldst_port0_data_len$11 , \ldst_port0_addr_i$12 , \ldst_port0_addr_i_ok$13 , \ldst_port0_addr_ok_o$14 , \ldst_port0_ld_data_o$15 , \ldst_port0_ld_data_o_ok$16 , \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 , \ldst_port0_exc_$signal$19 , coresync_clk);
+module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$1 , \ldst_port0_is_st_i$2 , \ldst_port0_busy_o$3 , \ldst_port0_data_len$4 , \ldst_port0_addr_i$5 , \ldst_port0_addr_i_ok$6 , \ldst_port0_addr_ok_o$7 , \ldst_port0_ld_data_o$8 , \ldst_port0_ld_data_o_ok$9 , \ldst_port0_st_data_i_ok$10 , \ldst_port0_st_data_i$11 , \ldst_port0_exc_happened$12 , coresync_clk);
   reg \initial  = 0;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *)
-  wire \$20 ;
+  wire \$13 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
-  wire \$22 ;
+  wire \$15 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
-  wire \$24 ;
+  wire \$17 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *)
-  wire \$26 ;
+  wire \$19 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *)
-  wire \$28 ;
+  wire \$21 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *)
-  wire [95:0] \$33 ;
+  wire [95:0] \$26 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *)
-  wire [95:0] \$34 ;
+  wire [95:0] \$27 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
   input coresync_clk;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
   input coresync_rst;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
-  reg \idx_l$23  = 1'h0;
+  reg \idx_l$16  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
-  reg \idx_l$23$next ;
+  reg \idx_l$16$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
   wire idx_l_q_idx_l;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
@@ -150974,126 +150974,126 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   input [95:0] ldst_port0_addr_i;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  output [47:0] \ldst_port0_addr_i$12 ;
-  reg [47:0] \ldst_port0_addr_i$12 ;
+  output [47:0] \ldst_port0_addr_i$5 ;
+  reg [47:0] \ldst_port0_addr_i$5 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   input ldst_port0_addr_i_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  output \ldst_port0_addr_i_ok$13 ;
-  reg \ldst_port0_addr_i_ok$13 ;
+  output \ldst_port0_addr_i_ok$6 ;
+  reg \ldst_port0_addr_i_ok$6 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *)
   output ldst_port0_addr_ok_o;
   reg ldst_port0_addr_ok_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *)
-  input \ldst_port0_addr_ok_o$14 ;
+  input \ldst_port0_addr_ok_o$7 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *)
   output ldst_port0_busy_o;
   reg ldst_port0_busy_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *)
-  input \ldst_port0_busy_o$10 ;
+  input \ldst_port0_busy_o$3 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *)
   reg ldst_port0_cache_paradox;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *)
-  wire \ldst_port0_cache_paradox$45 ;
+  wire \ldst_port0_cache_paradox$38 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   input [3:0] ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
-  output [3:0] \ldst_port0_data_len$11 ;
-  reg [3:0] \ldst_port0_data_len$11 ;
+  output [3:0] \ldst_port0_data_len$4 ;
+  reg [3:0] \ldst_port0_data_len$4 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal ;
-  reg \ldst_port0_exc_$signal ;
+  output ldst_port0_exc_alignment;
+  reg ldst_port0_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$1 ;
-  reg \ldst_port0_exc_$signal$1 ;
+  wire \ldst_port0_exc_alignment$29 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$19 ;
+  output ldst_port0_exc_badtree;
+  reg ldst_port0_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$2 ;
-  reg \ldst_port0_exc_$signal$2 ;
+  wire \ldst_port0_exc_badtree$32 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$3 ;
-  reg \ldst_port0_exc_$signal$3 ;
+  output ldst_port0_exc_happened;
+  reg ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$36 ;
+  input \ldst_port0_exc_happened$12 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$37 ;
+  output ldst_port0_exc_instr_fault;
+  reg ldst_port0_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$38 ;
+  wire \ldst_port0_exc_instr_fault$30 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$39 ;
+  output ldst_port0_exc_invalid;
+  reg ldst_port0_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$4 ;
-  reg \ldst_port0_exc_$signal$4 ;
+  wire \ldst_port0_exc_invalid$31 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$40 ;
+  output ldst_port0_exc_perm_error;
+  reg ldst_port0_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$41 ;
+  wire \ldst_port0_exc_perm_error$33 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \ldst_port0_exc_$signal$42 ;
+  output ldst_port0_exc_rc_error;
+  reg ldst_port0_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$5 ;
-  reg \ldst_port0_exc_$signal$5 ;
+  wire \ldst_port0_exc_rc_error$34 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$6 ;
-  reg \ldst_port0_exc_$signal$6 ;
+  output ldst_port0_exc_segment_fault;
+  reg ldst_port0_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \ldst_port0_exc_$signal$7 ;
-  reg \ldst_port0_exc_$signal$7 ;
+  wire \ldst_port0_exc_segment_fault$35 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" *)
   reg ldst_port0_go_die_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" *)
-  wire \ldst_port0_go_die_i$32 ;
+  wire \ldst_port0_go_die_i$25 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" *)
   reg ldst_port0_is_dcbz;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" *)
-  wire \ldst_port0_is_dcbz$31 ;
+  wire \ldst_port0_is_dcbz$24 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   input ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
-  output \ldst_port0_is_ld_i$8 ;
-  reg \ldst_port0_is_ld_i$8 ;
+  output \ldst_port0_is_ld_i$1 ;
+  reg \ldst_port0_is_ld_i$1 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" *)
   reg ldst_port0_is_nc;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" *)
-  wire \ldst_port0_is_nc$30 ;
+  wire \ldst_port0_is_nc$23 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
   input ldst_port0_is_st_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
-  output \ldst_port0_is_st_i$9 ;
-  reg \ldst_port0_is_st_i$9 ;
+  output \ldst_port0_is_st_i$2 ;
+  reg \ldst_port0_is_st_i$2 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   output [63:0] ldst_port0_ld_data_o;
   reg [63:0] ldst_port0_ld_data_o;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  input [63:0] \ldst_port0_ld_data_o$15 ;
+  input [63:0] \ldst_port0_ld_data_o$8 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   output ldst_port0_ld_data_o_ok;
   reg ldst_port0_ld_data_o_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  input \ldst_port0_ld_data_o_ok$16 ;
+  input \ldst_port0_ld_data_o_ok$9 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *)
   reg ldst_port0_ldst_error;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *)
-  wire \ldst_port0_ldst_error$44 ;
+  wire \ldst_port0_ldst_error$37 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *)
   reg ldst_port0_mmu_done;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *)
-  wire \ldst_port0_mmu_done$43 ;
+  wire \ldst_port0_mmu_done$36 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *)
   input ldst_port0_msr_pr;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *)
-  reg \ldst_port0_msr_pr$35 ;
+  reg \ldst_port0_msr_pr$28 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   input [63:0] ldst_port0_st_data_i;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  output [63:0] \ldst_port0_st_data_i$18 ;
-  reg [63:0] \ldst_port0_st_data_i$18 ;
+  output [63:0] \ldst_port0_st_data_i$11 ;
+  reg [63:0] \ldst_port0_st_data_i$11 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   input ldst_port0_st_data_i_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  output \ldst_port0_st_data_i_ok$17 ;
-  reg \ldst_port0_st_data_i_ok$17 ;
+  output \ldst_port0_st_data_i_ok$10 ;
+  reg \ldst_port0_st_data_i_ok$10 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *)
   wire pick_i;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" *)
@@ -151110,14 +151110,14 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
   reg reset_l_r_reset;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
   reg reset_l_s_reset;
-  assign \$20  = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) ldst_port0_is_st_i;
-  assign \$24  = idx_l_q_idx_l ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) pick_o : \idx_l$23 ;
-  assign \$26  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) pick_n;
-  assign \$28  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) \ldst_port0_busy_o$10 ;
+  assign \$13  = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) ldst_port0_is_st_i;
+  assign \$17  = idx_l_q_idx_l ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) pick_o : \idx_l$16 ;
+  assign \$19  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) pick_n;
+  assign \$21  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) \ldst_port0_busy_o$3 ;
   always @(posedge coresync_clk)
     reset_delay <= reset_l_q_reset;
   always @(posedge coresync_clk)
-    \idx_l$23  <= \idx_l$23$next ;
+    \idx_l$16  <= \idx_l$16$next ;
   idx_l idx_l (
     .coresync_clk(coresync_clk),
     .coresync_rst(coresync_rst),
@@ -151139,12 +151139,12 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
   );
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_data_len$11  = 4'h0;
+    \ldst_port0_data_len$4  = 4'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_data_len$11  = ldst_port0_data_len;
+          \ldst_port0_data_len$4  = ldst_port0_data_len;
     endcase
   end
   always @* begin
@@ -151154,48 +151154,48 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_go_die_i = \ldst_port0_go_die_i$32 ;
+          ldst_port0_go_die_i = \ldst_port0_go_die_i$25 ;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_addr_i$12  = 48'h000000000000;
+    \ldst_port0_addr_i$5  = 48'h000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_addr_i$12  = \$34 [47:0];
+          \ldst_port0_addr_i$5  = \$27 [47:0];
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_addr_i_ok$13  = 1'h0;
+    \ldst_port0_addr_i_ok$6  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_addr_i_ok$13  = ldst_port0_addr_i_ok;
+          \ldst_port0_addr_i_ok$6  = ldst_port0_addr_i_ok;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_st_data_i$18  = 64'h0000000000000000;
-    \ldst_port0_st_data_i_ok$17  = 1'h0;
+    \ldst_port0_st_data_i$11  = 64'h0000000000000000;
+    \ldst_port0_st_data_i_ok$10  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          { \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18  } = { ldst_port0_st_data_i_ok, ldst_port0_st_data_i };
+          { \ldst_port0_st_data_i_ok$10 , \ldst_port0_st_data_i$11  } = { ldst_port0_st_data_i_ok, ldst_port0_st_data_i };
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_msr_pr$35  = 1'h0;
+    \ldst_port0_msr_pr$28  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_msr_pr$35  = ldst_port0_msr_pr;
+          \ldst_port0_msr_pr$28  = ldst_port0_msr_pr;
     endcase
   end
   always @* begin
@@ -151206,7 +151206,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          { ldst_port0_ld_data_o_ok, ldst_port0_ld_data_o } = { \ldst_port0_ld_data_o_ok$16 , \ldst_port0_ld_data_o$15  };
+          { ldst_port0_ld_data_o_ok, ldst_port0_ld_data_o } = { \ldst_port0_ld_data_o_ok$9 , \ldst_port0_ld_data_o$8  };
     endcase
   end
   always @* begin
@@ -151216,22 +151216,22 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_busy_o = \ldst_port0_busy_o$10 ;
+          ldst_port0_busy_o = \ldst_port0_busy_o$3 ;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \idx_l$23$next  = \idx_l$23 ;
+    \idx_l$16$next  = \idx_l$16 ;
     (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */
       1'h1:
-          \idx_l$23$next  = pick_o;
+          \idx_l$16$next  = pick_o;
     endcase
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
-          \idx_l$23$next  = 1'h0;
+          \idx_l$16$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -151241,24 +151241,24 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_addr_ok_o = \ldst_port0_addr_ok_o$14 ;
+          ldst_port0_addr_ok_o = \ldst_port0_addr_ok_o$7 ;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_exc_$signal  = 1'h0;
-    \ldst_port0_exc_$signal$1  = 1'h0;
-    \ldst_port0_exc_$signal$2  = 1'h0;
-    \ldst_port0_exc_$signal$3  = 1'h0;
-    \ldst_port0_exc_$signal$4  = 1'h0;
-    \ldst_port0_exc_$signal$5  = 1'h0;
-    \ldst_port0_exc_$signal$6  = 1'h0;
-    \ldst_port0_exc_$signal$7  = 1'h0;
+    ldst_port0_exc_alignment = 1'h0;
+    ldst_port0_exc_instr_fault = 1'h0;
+    ldst_port0_exc_invalid = 1'h0;
+    ldst_port0_exc_badtree = 1'h0;
+    ldst_port0_exc_perm_error = 1'h0;
+    ldst_port0_exc_rc_error = 1'h0;
+    ldst_port0_exc_segment_fault = 1'h0;
+    ldst_port0_exc_happened = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal  } = { \ldst_port0_exc_$signal$19 , \ldst_port0_exc_$signal$42 , \ldst_port0_exc_$signal$41 , \ldst_port0_exc_$signal$40 , \ldst_port0_exc_$signal$39 , \ldst_port0_exc_$signal$38 , \ldst_port0_exc_$signal$37 , \ldst_port0_exc_$signal$36  };
+          { ldst_port0_exc_happened, ldst_port0_exc_segment_fault, ldst_port0_exc_rc_error, ldst_port0_exc_perm_error, ldst_port0_exc_badtree, ldst_port0_exc_invalid, ldst_port0_exc_instr_fault, ldst_port0_exc_alignment } = { \ldst_port0_exc_happened$12 , \ldst_port0_exc_segment_fault$35 , \ldst_port0_exc_rc_error$34 , \ldst_port0_exc_perm_error$33 , \ldst_port0_exc_badtree$32 , \ldst_port0_exc_invalid$31 , \ldst_port0_exc_instr_fault$30 , \ldst_port0_exc_alignment$29  };
     endcase
   end
   always @* begin
@@ -151268,14 +151268,14 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_mmu_done = \ldst_port0_mmu_done$43 ;
+          ldst_port0_mmu_done = \ldst_port0_mmu_done$36 ;
     endcase
   end
   always @* begin
     if (\initial ) begin end
     idx_l_s_idx_l = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *)
-    casez (\$26 )
+    casez (\$19 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" */
       1'h1:
           idx_l_s_idx_l = 1'h1;
@@ -151288,7 +151288,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_ldst_error = \ldst_port0_ldst_error$44 ;
+          ldst_port0_ldst_error = \ldst_port0_ldst_error$37 ;
     endcase
   end
   always @* begin
@@ -151298,7 +151298,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_cache_paradox = \ldst_port0_cache_paradox$45 ;
+          ldst_port0_cache_paradox = \ldst_port0_cache_paradox$38 ;
     endcase
   end
   always @* begin
@@ -151319,7 +151319,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *)
-          casez (\$28 )
+          casez (\$21 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" */
             1'h1:
                 reset_l_s_reset = 1'h1;
@@ -151338,22 +151338,22 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_is_ld_i$8  = 1'h0;
+    \ldst_port0_is_ld_i$1  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_is_ld_i$8  = ldst_port0_is_ld_i;
+          \ldst_port0_is_ld_i$1  = ldst_port0_is_ld_i;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_is_st_i$9  = 1'h0;
+    \ldst_port0_is_st_i$2  = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          \ldst_port0_is_st_i$9  = ldst_port0_is_st_i;
+          \ldst_port0_is_st_i$2  = ldst_port0_is_st_i;
     endcase
   end
   always @* begin
@@ -151363,7 +151363,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_is_nc = \ldst_port0_is_nc$30 ;
+          ldst_port0_is_nc = \ldst_port0_is_nc$23 ;
     endcase
   end
   always @* begin
@@ -151373,26 +151373,26 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_
     casez (idx_l_q_idx_l)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */
       1'h1:
-          ldst_port0_is_dcbz = \ldst_port0_is_dcbz$31 ;
-    endcase
-  end
-  assign \$22  = \$24 ;
-  assign \$34  = ldst_port0_addr_i;
-  assign \ldst_port0_is_nc$30  = 1'h0;
-  assign \ldst_port0_is_dcbz$31  = 1'h0;
-  assign \ldst_port0_go_die_i$32  = 1'h0;
-  assign \ldst_port0_exc_$signal$36  = 1'h0;
-  assign \ldst_port0_exc_$signal$37  = 1'h0;
-  assign \ldst_port0_exc_$signal$38  = 1'h0;
-  assign \ldst_port0_exc_$signal$39  = 1'h0;
-  assign \ldst_port0_exc_$signal$40  = 1'h0;
-  assign \ldst_port0_exc_$signal$41  = 1'h0;
-  assign \ldst_port0_exc_$signal$42  = 1'h0;
-  assign \ldst_port0_mmu_done$43  = 1'h0;
-  assign \ldst_port0_ldst_error$44  = 1'h0;
-  assign \ldst_port0_cache_paradox$45  = 1'h0;
+          ldst_port0_is_dcbz = \ldst_port0_is_dcbz$24 ;
+    endcase
+  end
+  assign \$15  = \$17 ;
+  assign \$27  = ldst_port0_addr_i;
+  assign \ldst_port0_is_nc$23  = 1'h0;
+  assign \ldst_port0_is_dcbz$24  = 1'h0;
+  assign \ldst_port0_go_die_i$25  = 1'h0;
+  assign \ldst_port0_exc_alignment$29  = 1'h0;
+  assign \ldst_port0_exc_instr_fault$30  = 1'h0;
+  assign \ldst_port0_exc_invalid$31  = 1'h0;
+  assign \ldst_port0_exc_badtree$32  = 1'h0;
+  assign \ldst_port0_exc_perm_error$33  = 1'h0;
+  assign \ldst_port0_exc_rc_error$34  = 1'h0;
+  assign \ldst_port0_exc_segment_fault$35  = 1'h0;
+  assign \ldst_port0_mmu_done$36  = 1'h0;
+  assign \ldst_port0_ldst_error$37  = 1'h0;
+  assign \ldst_port0_cache_paradox$38  = 1'h0;
   assign \reset_delay$next  = reset_l_q_reset;
-  assign pick_i = \$20 ;
+  assign pick_i = \$13 ;
 endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.ld_active" *)
@@ -151459,198 +151459,198 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0" *)
 (* generator = "nMigen" *)
-module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \exc_o_$signal , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
+module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
   reg \initial  = 0;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *)
-  wire \$10 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
-  wire \$100 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *)
-  wire \$102 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *)
-  wire \$104 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *)
-  wire \$106 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *)
+  wire \$1 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *)
-  wire \$108 ;
+  wire \$101 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *)
-  wire \$110 ;
+  wire \$103 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *)
-  wire \$112 ;
+  wire \$105 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457" *)
-  wire \$114 ;
+  wire \$107 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *)
-  wire \$116 ;
+  wire \$109 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *)
+  wire [2:0] \$11 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *)
-  wire \$118 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *)
-  wire \$12 ;
+  wire \$111 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *)
-  wire \$120 ;
+  wire \$113 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *)
-  wire \$122 ;
+  wire \$115 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *)
-  wire \$124 ;
+  wire \$117 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
-  wire \$126 ;
+  wire \$119 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *)
-  wire \$128 ;
+  wire \$121 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
-  wire \$130 ;
+  wire \$123 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
-  wire \$132 ;
+  wire \$125 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
-  wire \$134 ;
+  wire \$127 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *)
-  wire \$136 ;
+  wire \$129 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *)
+  wire \$13 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *)
-  wire \$138 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *)
-  wire \$14 ;
+  wire \$131 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *)
-  wire \$140 ;
+  wire \$133 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$142 ;
+  wire \$135 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$144 ;
+  wire \$137 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$146 ;
+  wire \$139 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$147 ;
+  wire \$140 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$149 ;
+  wire \$142 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
-  wire \$152 ;
+  wire \$145 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *)
-  wire \$154 ;
+  wire \$147 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *)
-  wire \$156 ;
+  wire \$149 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *)
+  wire \$15 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *)
-  wire \$158 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *)
-  wire \$16 ;
+  wire \$151 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *)
-  wire \$160 ;
+  wire \$153 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *)
-  wire \$162 ;
+  wire \$155 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *)
-  wire \$164 ;
+  wire \$157 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *)
-  wire \$166 ;
+  wire \$159 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *)
-  wire [2:0] \$168 ;
+  wire [2:0] \$161 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *)
-  wire \$169 ;
+  wire \$162 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *)
-  wire [2:0] \$171 ;
+  wire [2:0] \$164 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *)
-  wire \$173 ;
+  wire \$166 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *)
-  wire \$175 ;
+  wire \$168 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *)
+  wire \$17 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *)
-  wire [95:0] \$177 ;
+  wire [95:0] \$170 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" *)
-  wire \$179 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *)
-  wire [2:0] \$18 ;
+  wire \$172 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$188 ;
+  wire [63:0] \$174 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$190 ;
+  wire [63:0] \$176 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$192 ;
+  wire [63:0] \$178 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *)
-  wire \$194 ;
+  wire \$180 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$196 ;
+  wire [63:0] \$182 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$198 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *)
-  wire \$20 ;
+  wire [63:0] \$184 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
-  wire [63:0] \$200 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *)
-  wire \$22 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *)
-  wire \$24 ;
+  wire [63:0] \$186 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:318" *)
-  wire \$26 ;
+  wire \$19 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:319" *)
-  wire \$28 ;
+  wire \$21 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *)
-  wire \$30 ;
+  wire \$23 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *)
-  wire \$32 ;
+  wire \$25 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *)
-  wire \$34 ;
+  wire \$27 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *)
-  wire \$36 ;
+  wire \$29 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *)
+  wire \$3 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *)
-  wire [1:0] \$38 ;
+  wire [1:0] \$31 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$39 ;
+  wire \$32 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *)
-  wire \$41 ;
+  wire \$34 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$43 ;
+  wire \$36 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$45 ;
+  wire \$38 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$47 ;
+  wire \$40 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *)
-  wire \$49 ;
+  wire \$42 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$51 ;
+  wire \$44 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *)
-  wire \$53 ;
+  wire \$46 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *)
-  wire [1:0] \$55 ;
+  wire [1:0] \$48 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *)
+  wire \$5 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" *)
-  wire \$57 ;
+  wire \$50 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:374" *)
-  wire \$59 ;
+  wire \$52 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *)
-  wire \$61 ;
+  wire \$54 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *)
-  wire \$63 ;
+  wire \$56 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
-  wire [63:0] \$65 ;
+  wire [63:0] \$58 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
-  wire [63:0] \$67 ;
+  wire [63:0] \$60 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:412" *)
-  wire [63:0] \$69 ;
+  wire [63:0] \$62 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417" *)
-  wire [63:0] \$71 ;
+  wire [63:0] \$64 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *)
-  wire [64:0] \$73 ;
+  wire [64:0] \$66 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *)
-  wire [64:0] \$74 ;
+  wire [64:0] \$67 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
-  wire [2:0] \$76 ;
+  wire [2:0] \$69 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *)
+  wire \$7 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
-  wire [1:0] \$78 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *)
-  wire \$8 ;
+  wire [1:0] \$71 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
-  wire [2:0] \$80 ;
+  wire [2:0] \$73 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
-  wire [2:0] \$82 ;
+  wire [2:0] \$75 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
-  wire [2:0] \$84 ;
+  wire [2:0] \$77 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *)
-  wire \$86 ;
+  wire \$79 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *)
-  wire \$88 ;
+  wire \$81 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *)
-  wire \$90 ;
+  wire \$83 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *)
-  wire \$92 ;
+  wire \$85 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *)
-  wire \$93 ;
+  wire \$86 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *)
-  wire \$96 ;
+  wire \$89 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *)
+  wire \$9 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
-  wire \$98 ;
+  wire \$91 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
+  wire \$93 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *)
+  wire \$95 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *)
+  wire \$97 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *)
+  wire \$99 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278" *)
   wire addr_ok;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *)
@@ -151724,21 +151724,21 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
   reg [63:0] \ea_r$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  output \exc_o_$signal ;
+  wire exc_o_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$181 ;
+  wire exc_o_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$182 ;
+  output exc_o_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$183 ;
+  wire exc_o_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$184 ;
+  wire exc_o_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$185 ;
+  wire exc_o_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$186 ;
+  wire exc_o_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \exc_o_$signal$187 ;
+  wire exc_o_segment_fault;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:116" *)
   wire ld_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" *)
@@ -151770,21 +151770,21 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   output [3:0] ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal ;
+  input ldst_port0_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$1 ;
+  input ldst_port0_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$2 ;
+  input ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$3 ;
+  input ldst_port0_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$4 ;
+  input ldst_port0_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$5 ;
+  input ldst_port0_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$6 ;
+  input ldst_port0_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal$7 ;
+  input ldst_port0_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   output ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -152268,104 +152268,104 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   reg \wri_l_r_wri$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
   wire wri_l_s_wri;
-  assign \$100  = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) \$98 ;
-  assign \$102  = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) adr_l_q_adr;
-  assign \$104  = \$102  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) cu_busy_o;
-  assign \$106  = \exc_o_$signal  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *) cu_shadown_i;
-  assign \$108  = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) cu_busy_o;
-  assign \$10  = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *) cu_go_die_i;
-  assign \$110  = \$108  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) rd_done;
-  assign \$112  = \$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) op_is_st;
-  assign \$114  = \$112  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457" *) cancel;
-  assign \$116  = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wri_l_q_wri;
-  assign \$118  = \$116  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cu_busy_o;
-  assign \$120  = \$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) lod_l_qn_lod;
-  assign \$122  = \$120  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) op_is_ld;
-  assign \$124  = \$122  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cancel;
-  assign \$126  = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cu_busy_o;
-  assign \$128  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
-  assign \$12  = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) cu_go_die_i;
-  assign \$130  = \$126  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$128 ;
-  assign \$132  = \$130  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) alu_valid;
-  assign \$134  = \$132  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cancel;
-  assign \$136  = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) p_st_go;
-  assign \$138  = \$136  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[0];
-  assign \$140  = \$138  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[1];
-  assign \$142  = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_busy_o;
-  assign \$144  = \$142  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cancel;
-  assign \$147  = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[0];
-  assign \$14  = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *) cu_go_die_i;
-  assign \$149  = \$147  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[1];
-  assign \$146  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$149 ;
-  assign \$152  = \$144  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$146 ;
-  assign \$154  = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) op_is_st;
-  assign \$156  = \$152  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) \$154 ;
-  assign \$158  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) ldst_port0_busy_o;
-  assign \$160  = \$158  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) op_is_ld;
-  assign \$162  = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) \$160 ;
-  assign \$164  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
-  assign \$166  = \$164  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *) cu_wr__go_i[1];
-  assign \$16  = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *) cu_go_die_i;
-  assign \$169  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
-  assign \$171  = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *) { \$169 , op_is_ld };
-  assign \$173  = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) cu_busy_o;
-  assign \$175  = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) cu_busy_o;
-  assign \$177  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) addr_r;
-  assign \$179  = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" *) lsd_l_q_lsd;
-  assign \$188  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0];
-  assign \$18  = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
-  assign \$190  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] };
-  assign \$192  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] };
-  assign \$194  = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) 2'h2;
-  assign \$196  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0];
-  assign \$198  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8] };
-  assign \$200  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] };
-  assign \$20  = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *) cu_go_die_i;
-  assign \$22  = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *) 7'h26;
-  assign \$24  = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *) 7'h25;
-  assign \$26  = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:318" *) cu_ad__go_i;
-  assign \$28  = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:319" *) cu_st__go_i;
-  assign \$30  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) alu_valid;
-  assign \$32  = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$30 ;
-  assign \$34  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) rda_any;
-  assign \$36  = \$32  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$34 ;
-  assign \$39  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o;
-  assign \$41  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
-  assign \$43  = \$39  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$41 ;
-  assign \$45  = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$43 ;
-  assign \$47  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o;
-  assign \$49  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
-  assign \$51  = \$47  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$49 ;
-  assign \$53  = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$51 ;
-  assign \$55  = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *) { \$45 , \$53  };
-  assign \$57  = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" *) op_is_st;
-  assign \$59  = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:374" *) p_st_go;
-  assign \$61  = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) p_st_go;
-  assign \$63  = \$61  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) ld_ok;
-  assign \$65  = ld_ok ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) ldd_o : ldo_r;
-  assign \$67  = alu_l_q_alu ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) alu_o : ea_r;
-  assign \$69  = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:412" *) 64'h0000000000000000 : src_r0;
-  assign \$71  = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417" *) oper_r__imm_data__data : src_r1;
-  assign \$74  = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *) src2_or_imm;
-  assign \$76  = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { cu_busy_o, cu_busy_o, cu_busy_o };
-  assign \$78  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { oper_r__imm_data__ok, oper_r__zero_a };
-  assign \$80  = \$76  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$78 ;
-  assign \$82  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rdmaskn_i;
-  assign \$84  = \$80  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$82 ;
-  assign \$86  = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o;
-  assign \$88  = \$86  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) op_is_st;
-  assign \$8  = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i;
-  assign \$90  = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_rd__go_i[1];
-  assign \$93  = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[1];
-  assign \$92  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$93 ;
-  assign \$96  = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$92 ;
-  assign \$98  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_rd__rel_o[2];
+  assign \$9  = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *) cu_go_die_i;
+  assign \$99  = exc_o_happened | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *) cu_shadown_i;
+  assign \$101  = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) cu_busy_o;
+  assign \$103  = \$101  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) rd_done;
+  assign \$105  = \$103  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) op_is_st;
+  assign \$107  = \$105  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457" *) cancel;
+  assign \$109  = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wri_l_q_wri;
+  assign \$111  = \$109  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cu_busy_o;
+  assign \$113  = \$111  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) lod_l_qn_lod;
+  assign \$115  = \$113  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) op_is_ld;
+  assign \$117  = \$115  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cancel;
+  assign \$11  = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
+  assign \$119  = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cu_busy_o;
+  assign \$121  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
+  assign \$123  = \$119  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$121 ;
+  assign \$125  = \$123  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) alu_valid;
+  assign \$127  = \$125  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cancel;
+  assign \$129  = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) p_st_go;
+  assign \$131  = \$129  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[0];
+  assign \$133  = \$131  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[1];
+  assign \$135  = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_busy_o;
+  assign \$137  = \$135  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cancel;
+  assign \$13  = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *) cu_go_die_i;
+  assign \$140  = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[0];
+  assign \$142  = \$140  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[1];
+  assign \$139  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$142 ;
+  assign \$145  = \$137  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$139 ;
+  assign \$147  = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) op_is_st;
+  assign \$149  = \$145  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) \$147 ;
+  assign \$151  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) ldst_port0_busy_o;
+  assign \$153  = \$151  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) op_is_ld;
+  assign \$155  = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) \$153 ;
+  assign \$157  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
+  assign \$15  = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *) 7'h26;
+  assign \$159  = \$157  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *) cu_wr__go_i[1];
+  assign \$162  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
+  assign \$164  = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *) { \$162 , op_is_ld };
+  assign \$166  = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) cu_busy_o;
+  assign \$168  = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) cu_busy_o;
+  assign \$170  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) addr_r;
+  assign \$172  = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" *) lsd_l_q_lsd;
+  assign \$174  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0];
+  assign \$176  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] };
+  assign \$178  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] };
+  assign \$17  = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *) 7'h25;
+  assign \$180  = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) 2'h2;
+  assign \$182  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0];
+  assign \$184  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8] };
+  assign \$186  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] };
+  assign \$1  = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i;
+  assign \$19  = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:318" *) cu_ad__go_i;
+  assign \$21  = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:319" *) cu_st__go_i;
+  assign \$23  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) alu_valid;
+  assign \$25  = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$23 ;
+  assign \$27  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) rda_any;
+  assign \$29  = \$25  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$27 ;
+  assign \$32  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o;
+  assign \$34  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
+  assign \$36  = \$32  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$34 ;
+  assign \$38  = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$36 ;
+  assign \$3  = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *) cu_go_die_i;
+  assign \$40  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o;
+  assign \$42  = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1;
+  assign \$44  = \$40  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$42 ;
+  assign \$46  = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$44 ;
+  assign \$48  = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *) { \$38 , \$46  };
+  assign \$50  = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" *) op_is_st;
+  assign \$52  = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:374" *) p_st_go;
+  assign \$54  = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) p_st_go;
+  assign \$56  = \$54  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) ld_ok;
+  assign \$58  = ld_ok ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) ldd_o : ldo_r;
+  assign \$5  = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) cu_go_die_i;
+  assign \$60  = alu_l_q_alu ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) alu_o : ea_r;
+  assign \$62  = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:412" *) 64'h0000000000000000 : src_r0;
+  assign \$64  = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417" *) oper_r__imm_data__data : src_r1;
+  assign \$67  = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *) src2_or_imm;
+  assign \$69  = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { cu_busy_o, cu_busy_o, cu_busy_o };
+  assign \$71  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { oper_r__imm_data__ok, oper_r__zero_a };
+  assign \$73  = \$69  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$71 ;
+  assign \$75  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rdmaskn_i;
+  assign \$77  = \$73  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$75 ;
+  assign \$7  = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *) cu_go_die_i;
+  assign \$79  = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o;
+  assign \$81  = \$79  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) op_is_st;
+  assign \$83  = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_rd__go_i[1];
+  assign \$86  = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[1];
+  assign \$85  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$86 ;
+  assign \$89  = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$85 ;
+  assign \$91  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_rd__rel_o[2];
+  assign \$93  = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) \$91 ;
+  assign \$95  = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) adr_l_q_adr;
+  assign \$97  = \$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) cu_busy_o;
   always @(posedge coresync_clk)
     ldst_port0_addr_i_ok <= \ldst_port0_addr_i_ok$next ;
   always @(posedge coresync_clk)
-    ldst_port0_addr_i <= \$177 ;
+    ldst_port0_addr_i <= \$170 ;
   always @(posedge coresync_clk)
-    alu_ok <= \$96 ;
+    alu_ok <= \$89 ;
   always @(posedge coresync_clk)
     ea_r <= \ea_r$next ;
   always @(posedge coresync_clk)
@@ -152519,7 +152519,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
       1'h1:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *)
-          casez (\$194 )
+          casez (\$180 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */
             1'h1:
                 ldd_o = { revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15:0] };
@@ -152543,13 +152543,13 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
           casez (oper_r__data_len)
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h1:
-                stdata_r = \$196 ;
+                stdata_r = \$182 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h2:
-                stdata_r = \$198 ;
+                stdata_r = \$184 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h4:
-                stdata_r = \$200 ;
+                stdata_r = \$186 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h8:
                 stdata_r = { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24], src_r2[39:32], src_r2[47:40], src_r2[55:48], src_r2[63:56] };
@@ -152616,7 +152616,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   end
   always @* begin
     if (\initial ) begin end
-    \wri_l_r_wri$next  = \$38 [0];
+    \wri_l_r_wri$next  = \$31 [0];
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
@@ -152643,7 +152643,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   end
   always @* begin
     if (\initial ) begin end
-    \sto_l_r_sto$next  = \$59 ;
+    \sto_l_r_sto$next  = \$52 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
@@ -152652,7 +152652,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   end
   always @* begin
     if (\initial ) begin end
-    \lsd_l_r_lsd$next  = \$63 ;
+    \lsd_l_r_lsd$next  = \$56 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
@@ -152789,7 +152789,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
     if (\initial ) begin end
     dest2_o = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *)
-    casez (\$166 )
+    casez (\$159 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" */
       1'h1:
           dest2_o = addr_r;
@@ -152797,7 +152797,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
   end
   always @* begin
     if (\initial ) begin end
-    \ldst_port0_addr_i_ok$next  = \$179 ;
+    \ldst_port0_addr_i_ok$next  = \$172 ;
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (coresync_rst)
       1'h1:
@@ -152815,13 +152815,13 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
           casez (oper_r__data_len)
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h1:
-                lddata_r = \$188 ;
+                lddata_r = \$174 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h2:
-                lddata_r = \$190 ;
+                lddata_r = \$176 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h4:
-                lddata_r = \$192 ;
+                lddata_r = \$178 ;
             /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */
             4'h8:
                 lddata_r = { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24], ldst_port0_ld_data_o[39:32], ldst_port0_ld_data_o[47:40], ldst_port0_ld_data_o[55:48], ldst_port0_ld_data_o[63:56] };
@@ -152841,67 +152841,67 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i,
           revnorev = ldst_port0_ld_data_o;
     endcase
   end
-  assign \$38  = \$55 ;
-  assign \$73  = \$74 ;
-  assign \$168  = \$171 ;
+  assign \$31  = \$48 ;
+  assign \$66  = \$67 ;
+  assign \$161  = \$164 ;
   assign cu_go_die_i = 1'h0;
   assign cu_shadown_i = 1'h1;
   assign ldst_port0_st_data_i_ok = cu_st__go_i;
   assign ld_ok = ldst_port0_ld_data_o_ok;
   assign ldst_port0_msr_pr = oper_r__msr[14];
   assign addr_ok = ldst_port0_addr_ok_o;
-  assign { \exc_o_$signal , \exc_o_$signal$187 , \exc_o_$signal$186 , \exc_o_$signal$185 , \exc_o_$signal$184 , \exc_o_$signal$183 , \exc_o_$signal$182 , \exc_o_$signal$181  } = { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal  };
-  assign \ldst_port0_addr_i$next  = \$177 ;
+  assign { exc_o_happened, exc_o_segment_fault, exc_o_rc_error, exc_o_perm_error, exc_o_badtree, exc_o_invalid, exc_o_instr_fault, exc_o_alignment } = { ldst_port0_exc_happened, ldst_port0_exc_segment_fault, ldst_port0_exc_rc_error, ldst_port0_exc_perm_error, ldst_port0_exc_badtree, ldst_port0_exc_invalid, ldst_port0_exc_instr_fault, ldst_port0_exc_alignment };
+  assign \ldst_port0_addr_i$next  = \$170 ;
   assign ldst_port0_data_len = oper_r__data_len;
-  assign ldst_port0_is_st_i = \$175 ;
-  assign ldst_port0_is_ld_i = \$173 ;
-  assign cu_wrmask_o = \$171 [1:0];
+  assign ldst_port0_is_st_i = \$168 ;
+  assign ldst_port0_is_ld_i = \$166 ;
+  assign cu_wrmask_o = \$164 [1:0];
   assign ea = dest2_o;
   assign o = dest1_o;
-  assign cu_done_o = \$162 ;
-  assign wr_reset = \$156 ;
-  assign wr_any = \$140 ;
-  assign cu_wr__rel_o[1] = \$134 ;
-  assign cu_wr__rel_o[0] = \$124 ;
-  assign cu_st__rel_o = \$114 ;
-  assign cancel = \$106 ;
-  assign cu_ad__rel_o = \$104 ;
-  assign rd_done = \$100 ;
-  assign alu_valid = \$96 ;
-  assign rda_any = \$90 ;
-  assign cu_rd__rel_o[2] = \$88 ;
-  assign cu_rd__rel_o[1:0] = \$84 [1:0];
+  assign cu_done_o = \$155 ;
+  assign wr_reset = \$149 ;
+  assign wr_any = \$133 ;
+  assign cu_wr__rel_o[1] = \$127 ;
+  assign cu_wr__rel_o[0] = \$117 ;
+  assign cu_st__rel_o = \$107 ;
+  assign cancel = \$99 ;
+  assign cu_ad__rel_o = \$97 ;
+  assign rd_done = \$93 ;
+  assign alu_valid = \$89 ;
+  assign rda_any = \$83 ;
+  assign cu_rd__rel_o[2] = \$81 ;
+  assign cu_rd__rel_o[1:0] = \$77 [1:0];
   assign cu_busy_o = opc_l_q_opc;
   assign \alu_ok$next  = alu_valid;
-  assign alu_o = \$74 [63:0];
-  assign src2_or_imm = \$71 ;
-  assign src1_or_z = \$69 ;
-  assign addr_r = \$67 ;
-  assign ldd_r = \$65 ;
+  assign alu_o = \$67 [63:0];
+  assign src2_or_imm = \$64 ;
+  assign src1_or_z = \$62 ;
+  assign addr_r = \$60 ;
+  assign ldd_r = \$58 ;
   assign rst_l_r_rst = cu_issue_i;
   assign rst_l_s_rst = addr_ok;
   assign lsd_l_s_lsd = cu_issue_i;
-  assign sto_l_s_sto = \$57 ;
+  assign sto_l_s_sto = \$50 ;
   assign wri_l_s_wri = cu_issue_i;
   assign lod_l_r_lod = ld_ok;
   assign lod_l_s_lod = reset_i;
   assign adr_l_s_adr = reset_i;
-  assign alu_l_r_alu = \$36 ;
+  assign alu_l_r_alu = \$29 ;
   assign alu_l_s_alu = reset_i;
   assign st_o = op_is_st;
   assign ld_o = op_is_ld;
-  assign stwd_mem_o = \$28 ;
-  assign load_mem_o = \$26 ;
-  assign op_is_ld = \$24 ;
-  assign op_is_st = \$22 ;
+  assign stwd_mem_o = \$21 ;
+  assign load_mem_o = \$19 ;
+  assign op_is_ld = \$17 ;
+  assign op_is_st = \$15 ;
   assign \p_st_go$next  = cu_st__go_i;
-  assign reset_a = \$20 ;
-  assign reset_r = \$18 ;
-  assign reset_s = \$16 ;
-  assign reset_u = \$14 ;
-  assign reset_w = \$12 ;
-  assign reset_o = \$10 ;
-  assign reset_i = \$8 ;
+  assign reset_a = \$13 ;
+  assign reset_r = \$11 ;
+  assign reset_s = \$9 ;
+  assign reset_u = \$7 ;
+  assign reset_w = \$5 ;
+  assign reset_o = \$3 ;
+  assign reset_i = \$1 ;
 endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" *)
@@ -160251,12 +160251,6 @@ endmodule
 (* generator = "nMigen" *)
 module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , o, o_ok, \fast1$16 , fast1_ok, \fast2$17 , fast2_ok, fast3, fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, muxid);
   reg \initial  = 0;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *)
-  wire \$100 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
-  wire \$102 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
-  wire \$104 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
   wire [63:0] \$18 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
@@ -160306,33 +160300,39 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
   wire [7:0] \$62 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
-  wire \$68 ;
+  wire \$65 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *)
-  wire [7:0] \$69 ;
+  wire [7:0] \$66 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
-  wire [63:0] \$72 ;
+  wire [63:0] \$69 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
-  wire [63:0] \$74 ;
+  wire [63:0] \$71 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
-  wire [63:0] \$76 ;
+  wire [63:0] \$73 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
-  wire \$82 ;
+  wire \$75 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
-  wire [7:0] \$83 ;
+  wire [7:0] \$76 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
-  wire [64:0] \$86 ;
+  wire [64:0] \$79 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *)
-  wire \$88 ;
+  wire \$81 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *)
-  wire \$90 ;
+  wire \$83 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
-  wire \$92 ;
+  wire \$85 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
-  wire \$94 ;
+  wire \$87 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *)
-  wire \$96 ;
+  wire \$89 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *)
-  wire \$98 ;
+  wire \$91 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *)
+  wire \$93 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
+  wire \$95 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
+  wire \$97 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" *)
   reg [63:0] a;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:146" *)
@@ -160670,24 +160670,21 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
   output [7:0] \trap_op__traptype$9 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal ;
+  reg trapexc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$65 ;
+  reg trapexc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$66 ;
+  reg trapexc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$67 ;
+  reg trapexc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$78 ;
+  reg trapexc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$79 ;
+  reg trapexc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$80 ;
+  reg trapexc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \trapexc_$signal$81 ;
-  assign \$100  = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) 3'h2;
-  assign \$102  = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) 3'h0;
-  assign \$104  = \$100  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) \$102 ;
+  reg trapexc_segment_fault;
   assign \$18  = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0];
   assign \$20  = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0];
   assign \$22  = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) $signed(b_s);
@@ -160711,20 +160708,23 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
   assign \$57  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$58 ;
   assign \$62  = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
   assign \$61  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$62 ;
-  assign \$69  = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) 8'h80;
-  assign \$68  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$69 ;
-  assign \$72  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
-  assign \$74  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
-  assign \$76  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
-  assign \$83  = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
-  assign \$82  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$83 ;
-  assign \$86  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__msr;
-  assign \$88  = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) 7'h48;
-  assign \$90  = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) 3'h2;
-  assign \$92  = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) 3'h0;
-  assign \$94  = \$90  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) \$92 ;
-  assign \$96  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) trap_op__msr[60];
-  assign \$98  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) trap_op__insn[9];
+  assign \$66  = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) 8'h80;
+  assign \$65  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$66 ;
+  assign \$69  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+  assign \$71  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+  assign \$73  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+  assign \$76  = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
+  assign \$75  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$76 ;
+  assign \$79  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__msr;
+  assign \$81  = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) 7'h48;
+  assign \$83  = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) 3'h2;
+  assign \$85  = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) 3'h0;
+  assign \$87  = \$83  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) \$85 ;
+  assign \$89  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) trap_op__msr[60];
+  assign \$91  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) trap_op__insn[9];
+  assign \$93  = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) 3'h2;
+  assign \$95  = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) 3'h0;
+  assign \$97  = \$93  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) \$95 ;
   always @* begin
     if (\initial ) begin end
     (* full_case = 32'd1 *)
@@ -160912,14 +160912,14 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */
                   1'h1:
                     begin
-                      \fast2$17 [30] = \trapexc_$signal ;
-                      \fast2$17 [28] = \trapexc_$signal$65 ;
-                      \fast2$17 [19] = \trapexc_$signal$66 ;
-                      \fast2$17 [18] = \trapexc_$signal$67 ;
+                      \fast2$17 [30] = trapexc_invalid;
+                      \fast2$17 [28] = trapexc_perm_error;
+                      \fast2$17 [19] = trapexc_badtree;
+                      \fast2$17 [18] = trapexc_rc_error;
                     end
                 endcase
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *)
-                casez (\$68 )
+                casez (\$65 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" */
                   1'h1:
                       \fast2$17 [19] = 1'h1;
@@ -160993,7 +160993,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
           casez (should_trap)
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
             1'h1:
-                fast3 = \$74 ;
+                fast3 = \$71 ;
           endcase
       /* \nmigen.decoding  = "OP_MTMSRD/72|OP_MTMSR/74" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
@@ -161010,7 +161010,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
       /* \nmigen.decoding  = "OP_SC/73" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */
       7'h49:
-          fast3 = \$76 ;
+          fast3 = \$73 ;
     endcase
   end
   always @* begin
@@ -161060,14 +161060,14 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
   end
   always @* begin
     if (\initial ) begin end
-    \trapexc_$signal$78  = 1'h0;
-    \trapexc_$signal$79  = 1'h0;
-    \trapexc_$signal  = 1'h0;
-    \trapexc_$signal$66  = 1'h0;
-    \trapexc_$signal$65  = 1'h0;
-    \trapexc_$signal$67  = 1'h0;
-    \trapexc_$signal$80  = 1'h0;
-    \trapexc_$signal$81  = 1'h0;
+    trapexc_alignment = 1'h0;
+    trapexc_instr_fault = 1'h0;
+    trapexc_invalid = 1'h0;
+    trapexc_badtree = 1'h0;
+    trapexc_perm_error = 1'h0;
+    trapexc_rc_error = 1'h0;
+    trapexc_segment_fault = 1'h0;
+    trapexc_happened = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *)
     casez (trap_op__insn_type)
       /* \nmigen.decoding  = "OP_TRAP/63" */
@@ -161078,10 +161078,10 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
-                casez (\$82 )
+                casez (\$75 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */
                   1'h1:
-                      { \trapexc_$signal$81 , \trapexc_$signal$80 , \trapexc_$signal$67 , \trapexc_$signal$65 , \trapexc_$signal$66 , \trapexc_$signal , \trapexc_$signal$79 , \trapexc_$signal$78  } = trap_op__ldst_exc;
+                      { trapexc_happened, trapexc_segment_fault, trapexc_rc_error, trapexc_perm_error, trapexc_badtree, trapexc_invalid, trapexc_instr_fault, trapexc_alignment } = trap_op__ldst_exc;
                 endcase
           endcase
     endcase
@@ -161125,7 +161125,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
       7'h48, 7'h4a:
         begin
-          { msr_ok, msr } = \$86 ;
+          { msr_ok, msr } = \$79 ;
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:239" *)
           casez (trap_op__insn[21])
@@ -161140,7 +161140,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
               begin
                 (* full_case = 32'd1 *)
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *)
-                casez (\$88 )
+                casez (\$81 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" */
                   1'h1:
                     begin
@@ -161148,7 +161148,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
                       msr[59:13] = ra[59:13];
                       msr[63:61] = ra[63:61];
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
-                      casez (\$94 )
+                      casez (\$87 )
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" */
                         1'h1:
                             msr[34:32] = trap_op__msr[34:32];
@@ -161174,7 +161174,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
               end
           endcase
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *)
-          casez (\$96 )
+          casez (\$89 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" */
             1'h1:
               begin
@@ -161198,7 +161198,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
           msr[26:22] = fast2[26:22];
           msr[63:31] = fast2[63:31];
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *)
-          casez (\$98 )
+          casez (\$91 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" */
             1'h1:
                 (* full_case = 32'd1 *)
@@ -161223,7 +161223,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m
               end
           endcase
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
-          casez (\$104 )
+          casez (\$97 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" */
             1'h1:
                 msr[34:32] = trap_op__msr[34:32];
@@ -173604,7 +173604,7 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem" *)
 (* generator = "nMigen" *)
-module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_busy_o, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, x_mask_i, x_addr_i, ldst_port0_addr_ok_o, m_ld_data_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i_ok, ldst_port0_st_data_i, x_st_data_i, x_busy_o, \ldst_port0_exc_$signal , x_ld_i, x_st_i, m_valid_i, x_valid_i, coresync_clk);
+module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_busy_o, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, x_mask_i, x_addr_i, ldst_port0_addr_ok_o, m_ld_data_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i_ok, ldst_port0_st_data_i, x_st_data_i, x_busy_o, ldst_port0_exc_happened, x_ld_i, x_st_i, m_valid_i, x_valid_i, coresync_clk);
   reg \initial  = 0;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *)
   wire \$1 ;
@@ -173758,7 +173758,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *)
   input [3:0] ldst_port0_data_len;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  input \ldst_port0_exc_$signal ;
+  input ldst_port0_exc_happened;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
   input ldst_port0_is_ld_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *)
@@ -174338,7 +174338,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu
     if (\initial ) begin end
     busy_l_r_busy = 1'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:305" *)
-    casez (\ldst_port0_exc_$signal )
+    casez (ldst_port0_exc_happened)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:305" */
       1'h1:
           busy_l_r_busy = 1'h1;
@@ -207095,7 +207095,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  spblock_512w64b8w \spblock_512w64b8w_%s  (
+  spblock_512w64b8w spblock_512w64b8w_0 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -207239,7 +207239,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-  spblock_512w64b8w \spblock_512w64b8w_%s  (
+  spblock_512w64b8w spblock_512w64b8w_1 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -207383,7 +207383,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-  spblock_512w64b8w \spblock_512w64b8w_%s  (
+  spblock_512w64b8w spblock_512w64b8w_2 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -207527,7 +207527,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-  spblock_512w64b8w \spblock_512w64b8w_%s  (
+  spblock_512w64b8w spblock_512w64b8w_3 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -209866,264 +209866,264 @@ endmodule
 (* generator = "nMigen" *)
 module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk);
   reg \initial  = 0;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$100 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
-  wire \$102 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
-  wire [64:0] \$104 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
-  wire [64:0] \$105 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
-  wire [31:0] \$107 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *)
-  wire [6:0] \$108 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
-  wire [31:0] \$111 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
-  wire [64:0] \$112 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
-  wire [64:0] \$113 ;
-  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *)
-  wire [6:0] \$115 ;
+  wire [6:0] \$101 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$118 ;
+  wire \$104 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$120 ;
+  wire \$106 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$122 ;
+  wire \$108 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
+  wire \$11 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$124 ;
+  wire \$110 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$126 ;
+  wire \$112 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$128 ;
+  wire \$114 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-  wire \$130 ;
+  wire \$116 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$132 ;
+  wire \$118 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$134 ;
+  wire \$120 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
-  wire [7:0] \$136 ;
+  wire [7:0] \$122 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
-  wire [7:0] \$137 ;
+  wire [7:0] \$123 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
-  wire [7:0] \$139 ;
+  wire [7:0] \$125 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
-  wire [7:0] \$140 ;
+  wire [7:0] \$126 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *)
-  wire \$142 ;
+  wire \$128 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+  wire [2:0] \$13 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$144 ;
+  wire \$130 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$146 ;
+  wire \$132 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$148 ;
+  wire \$134 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$150 ;
+  wire \$136 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$152 ;
+  wire \$138 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+  wire [2:0] \$14 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$154 ;
+  wire \$140 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$156 ;
+  wire \$142 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$158 ;
+  wire \$144 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *)
-  wire \$160 ;
+  wire \$146 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$162 ;
+  wire \$148 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  wire \$150 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  wire \$152 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+  wire \$154 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  wire \$156 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  wire \$158 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+  wire \$16 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  wire \$160 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  wire \$162 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$164 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$166 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$168 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$170 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$172 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$174 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$176 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$178 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+  wire \$18 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$180 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$182 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
   wire \$184 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$186 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
+  wire [2:0] \$185 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$188 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$190 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$192 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$194 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$196 ;
-  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$198 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
-  wire [2:0] \$199 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
+  wire \$20 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+  wire \$200 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
   wire \$202 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
   wire \$204 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$206 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$208 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
   wire \$210 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$212 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$214 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$216 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
   wire \$218 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$220 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *)
+  wire [2:0] \$219 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
+  wire \$22 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
   wire \$222 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
   wire \$224 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
   wire \$226 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$228 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
-  wire \$23 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
   wire \$230 ;
-  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
-  wire \$232 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *)
-  wire [2:0] \$233 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$236 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$238 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-  wire \$240 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$242 ;
+  wire \$232 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$244 ;
+  wire \$234 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$246 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$248 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
-  wire \$25 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$250 ;
+  wire \$236 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$252 ;
+  wire \$238 ;
+  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
+  wire \$24 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
-  wire \$254 ;
+  wire \$240 ;
   (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *)
-  wire [63:0] \$256 ;
+  wire [63:0] \$242 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *)
-  wire \$258 ;
+  wire \$244 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-  wire \$260 ;
+  wire \$246 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-  wire \$262 ;
+  wire \$248 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [63:0] \$264 ;
+  wire [63:0] \$250 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  wire [63:0] \$266 ;
+  wire [63:0] \$252 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
-  wire [64:0] \$268 ;
+  wire [64:0] \$254 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
-  wire [64:0] \$269 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
-  wire [2:0] \$27 ;
+  wire [64:0] \$255 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
-  wire [64:0] \$271 ;
+  wire [64:0] \$257 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
-  wire [64:0] \$272 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
-  wire [2:0] \$28 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
-  wire \$30 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
-  wire \$32 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
-  wire \$34 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$36 ;
-  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
-  wire \$38 ;
+  wire [64:0] \$258 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$40 ;
+  wire \$26 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
-  wire \$42 ;
+  wire \$28 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$44 ;
+  wire \$30 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$46 ;
+  wire \$32 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$48 ;
+  wire \$34 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
-  wire \$50 ;
+  wire \$36 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$52 ;
+  wire \$38 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [63:0] \$54 ;
+  wire [63:0] \$40 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-  wire \$56 ;
+  wire \$42 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$58 ;
+  wire \$44 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$60 ;
+  wire \$46 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$62 ;
+  wire \$48 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$64 ;
+  wire \$50 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$66 ;
+  wire \$52 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$68 ;
+  wire \$54 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$70 ;
+  wire \$56 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$72 ;
+  wire \$58 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-  wire \$74 ;
+  wire \$60 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$76 ;
+  wire \$62 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$78 ;
+  wire \$64 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$80 ;
+  wire \$66 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$82 ;
+  wire \$68 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-  wire \$84 ;
+  wire \$70 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$86 ;
+  wire \$72 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-  wire \$88 ;
+  wire \$74 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$90 ;
+  wire \$76 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$92 ;
+  wire \$78 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-  wire \$94 ;
+  wire \$80 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-  wire \$96 ;
+  wire \$82 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
-  wire \$98 ;
+  wire \$84 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *)
+  wire \$86 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+  wire \$88 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
+  wire \$9 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
+  wire [64:0] \$90 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *)
+  wire [64:0] \$91 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
+  wire [31:0] \$93 ;
+  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *)
+  wire [6:0] \$94 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
+  wire [31:0] \$97 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
+  wire [64:0] \$98 ;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *)
+  wire [64:0] \$99 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
   input TAP_bus__tck;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
@@ -210143,9 +210143,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
   input core_bigendian_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
-  reg \core_bigendian_i$10  = 1'h0;
+  reg \core_bigendian_i$3  = 1'h0;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
-  reg \core_bigendian_i$10$next ;
+  reg \core_bigendian_i$3$next ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   wire [63:0] core_cia__data_o;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -210191,37 +210191,37 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   reg [7:0] \core_core_core_cr_wr$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal  = 1'h0;
+  reg core_core_core_exc_alignment = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$3  = 1'h0;
+  reg \core_core_core_exc_alignment$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$3$next ;
+  reg core_core_core_exc_badtree = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$4  = 1'h0;
+  reg \core_core_core_exc_badtree$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$4$next ;
+  reg core_core_core_exc_happened = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$5  = 1'h0;
+  reg \core_core_core_exc_happened$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$5$next ;
+  reg core_core_core_exc_instr_fault = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$6  = 1'h0;
+  reg \core_core_core_exc_instr_fault$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$6$next ;
+  reg core_core_core_exc_invalid = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$7  = 1'h0;
+  reg \core_core_core_exc_invalid$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$7$next ;
+  reg core_core_core_exc_perm_error = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$8  = 1'h0;
+  reg \core_core_core_exc_perm_error$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$8$next ;
+  reg core_core_core_exc_rc_error = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$9  = 1'h0;
+  reg \core_core_core_exc_rc_error$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$9$next ;
+  reg core_core_core_exc_segment_fault = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  reg \core_core_core_exc_$signal$next ;
+  reg \core_core_core_exc_segment_fault$next ;
   (* enum_base_type = "Function" *)
   (* enum_value_000000000000000 = "NONE" *)
   (* enum_value_000000000000010 = "ALU" *)
@@ -210568,7 +210568,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   reg [63:0] core_data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  reg [63:0] \core_data_i$12 ;
+  reg [63:0] \core_data_i$5 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *)
   reg [63:0] core_dec = 64'h0000000000000000;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *)
@@ -210588,7 +210588,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *)
   reg \core_eint$next ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \core_exc_o_$signal ;
+  wire core_exc_o_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   reg core_fasto1_ok = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -210612,7 +210612,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   reg [3:0] core_issue__addr;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  reg [3:0] \core_issue__addr$13 ;
+  reg [3:0] \core_issue__addr$6 ;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   reg [63:0] core_issue__data_i;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
@@ -210652,7 +210652,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
   reg [2:0] core_wen;
   (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
-  reg [2:0] \core_wen$11 ;
+  reg [2:0] \core_wen$4 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *)
   reg core_xer_out = 1'h0;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *)
@@ -210778,11 +210778,11 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [6:0] dec2_cr_in2;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire [6:0] \dec2_cr_in2$14 ;
+  wire [6:0] \dec2_cr_in2$7 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire dec2_cr_in2_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
-  wire \dec2_cr_in2_ok$15 ;
+  wire \dec2_cr_in2_ok$8 ;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [6:0] dec2_cr_out;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -210840,21 +210840,21 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire dec2_ea_ok;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal ;
+  wire dec2_exc_alignment;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$16 ;
+  wire dec2_exc_badtree;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$17 ;
+  wire dec2_exc_happened;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$18 ;
+  wire dec2_exc_instr_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$19 ;
+  wire dec2_exc_invalid;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$20 ;
+  wire dec2_exc_perm_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$21 ;
+  wire dec2_exc_rc_error;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
-  wire \dec2_exc_$signal$22 ;
+  wire dec2_exc_segment_fault;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
   wire [2:0] dec2_fast1;
   (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *)
@@ -212086,128 +212086,128 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   wire [7:0] xics_ics_icp_o_pri;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
   wire [3:0] xics_ics_icp_o_src;
-  assign \$100  = \$98  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
-  assign \$102  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
-  assign \$105  = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4;
-  assign \$108  = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
-  assign \$107  = imem_f_instr_o >> \$108 ;
-  assign \$113  = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4;
-  assign \$115  = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
-  assign \$111  = imem_f_instr_o >> \$115 ;
-  assign \$118  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$120  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$122  = \$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$120 ;
-  assign \$124  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$126  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$128  = \$124  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$126 ;
-  assign \$130  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
-  assign \$132  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
-  assign \$134  = \$132  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
-  assign \$137  = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1;
-  assign \$140  = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1;
-  assign \$142  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) \core_exc_o_$signal ;
-  assign \$144  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$146  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$148  = \$144  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$146 ;
-  assign \$150  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$152  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$154  = \$150  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$152 ;
-  assign \$156  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
-  assign \$158  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$156 ;
-  assign \$160  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) is_svp64_mode;
-  assign \$162  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$164  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$166  = \$162  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$164 ;
-  assign \$168  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
-  assign \$170  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
-  assign \$172  = \$170  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
-  assign \$174  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$176  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$178  = \$174  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$176 ;
-  assign \$180  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$182  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$184  = \$180  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$182 ;
-  assign \$186  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$188  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$190  = \$186  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$188 ;
-  assign \$192  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$194  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$196  = \$192  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$194 ;
-  assign \$199  = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 1'h1;
-  assign \$198  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$199 ;
-  assign \$202  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$204  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$206  = \$202  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$204 ;
-  assign \$208  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$210  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$212  = \$208  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$210 ;
-  assign \$214  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
-  assign \$216  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
-  assign \$218  = \$216  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
-  assign \$220  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$222  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$224  = \$220  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$222 ;
-  assign \$226  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$228  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$230  = \$226  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$228 ;
-  assign \$233  = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) 3'h4;
-  assign \$232  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$233 ;
-  assign \$236  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
-  assign \$238  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$236 ;
-  assign \$23  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
-  assign \$240  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
-  assign \$242  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$244  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$246  = \$242  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$244 ;
-  assign \$248  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$250  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$252  = \$248  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$250 ;
-  assign \$254  = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) dec2_cur_cur_vl;
-  assign \$256  = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
-  assign \$258  = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) 7'h01;
-  assign \$25  = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) 1'h0;
-  assign \$260  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
-  assign \$262  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
-  assign \$264  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
-  assign \$266  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
-  assign \$269  = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) 1'h1;
-  assign \$272  = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) 1'h1;
-  assign \$28  = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h1;
-  assign \$30  = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) dbg_core_rst_o;
-  assign \$32  = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) rst;
-  assign \$34  = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) \$32 ;
-  assign \$36  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
-  assign \$38  = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ;
-  assign \$40  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$42  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok;
-  assign \$44  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$46  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$48  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$50  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) svstate_i_ok;
-  assign \$52  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$54  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) svstate_i;
-  assign \$56  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
-  assign \$58  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$60  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$62  = \$58  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$60 ;
-  assign \$64  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
-  assign \$66  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$64 ;
-  assign \$68  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$70  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$72  = \$68  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$70 ;
-  assign \$74  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
-  assign \$76  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
-  assign \$78  = \$76  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
-  assign \$80  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
-  assign \$82  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
-  assign \$84  = \$80  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$82 ;
-  assign \$86  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
-  assign \$88  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$86 ;
-  assign \$90  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
-  assign \$92  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
-  assign \$94  = \$90  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$92 ;
-  assign \$96  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
-  assign \$98  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$9  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
+  assign \$99  = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4;
+  assign \$101  = \$98 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
+  assign \$97  = imem_f_instr_o >> \$101 ;
+  assign \$104  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$106  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$108  = \$104  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$106 ;
+  assign \$110  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$112  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$114  = \$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$112 ;
+  assign \$116  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
+  assign \$118  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$11  = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) 1'h0;
+  assign \$120  = \$118  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
+  assign \$123  = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1;
+  assign \$126  = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1;
+  assign \$128  = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) core_exc_o_happened;
+  assign \$130  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$132  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$134  = \$130  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$132 ;
+  assign \$136  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$138  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$140  = \$136  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$138 ;
+  assign \$142  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
+  assign \$144  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$142 ;
+  assign \$146  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) is_svp64_mode;
+  assign \$148  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$14  = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h1;
+  assign \$150  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$152  = \$148  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$150 ;
+  assign \$154  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
+  assign \$156  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$158  = \$156  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
+  assign \$160  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$162  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$164  = \$160  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$162 ;
+  assign \$166  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$168  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$16  = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) dbg_core_rst_o;
+  assign \$170  = \$166  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$168 ;
+  assign \$172  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$174  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$176  = \$172  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$174 ;
+  assign \$178  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$180  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$182  = \$178  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$180 ;
+  assign \$185  = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 1'h1;
+  assign \$184  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$185 ;
+  assign \$188  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$18  = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) rst;
+  assign \$190  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$192  = \$188  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$190 ;
+  assign \$194  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$196  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$198  = \$194  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$196 ;
+  assign \$200  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
+  assign \$202  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$204  = \$202  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
+  assign \$206  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$208  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$20  = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) \$18 ;
+  assign \$210  = \$206  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$208 ;
+  assign \$212  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$214  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$216  = \$212  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$214 ;
+  assign \$219  = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) 3'h4;
+  assign \$218  = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$219 ;
+  assign \$222  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
+  assign \$224  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$222 ;
+  assign \$226  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
+  assign \$228  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$22  = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
+  assign \$230  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$232  = \$228  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$230 ;
+  assign \$234  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$236  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$238  = \$234  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$236 ;
+  assign \$240  = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) dec2_cur_cur_vl;
+  assign \$242  = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
+  assign \$244  = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) 7'h01;
+  assign \$246  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
+  assign \$248  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o;
+  assign \$24  = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$22 ;
+  assign \$250  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
+  assign \$252  = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
+  assign \$255  = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) 1'h1;
+  assign \$258  = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) 1'h1;
+  assign \$26  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$28  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok;
+  assign \$30  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$32  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$34  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$36  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) svstate_i_ok;
+  assign \$38  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$40  = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) svstate_i;
+  assign \$42  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
+  assign \$44  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$46  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$48  = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$46 ;
+  assign \$50  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
+  assign \$52  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$50 ;
+  assign \$54  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$56  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$58  = \$54  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$56 ;
+  assign \$60  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
+  assign \$62  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$64  = \$62  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
+  assign \$66  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o;
+  assign \$68  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst;
+  assign \$70  = \$66  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$68 ;
+  assign \$72  = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0;
+  assign \$74  = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$72 ;
+  assign \$76  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o;
+  assign \$78  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst;
+  assign \$80  = \$76  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$78 ;
+  assign \$82  = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed;
+  assign \$84  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0;
+  assign \$86  = \$84  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last;
+  assign \$88  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read;
+  assign \$91  = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4;
+  assign \$94  = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
+  assign \$93  = imem_f_instr_o >> \$94 ;
   always @(posedge clk)
     fsm_state <= \fsm_state$next ;
   always @(posedge clk)
@@ -212345,7 +212345,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   always @(posedge clk)
     core_core_core_msr <= \core_core_core_msr$next ;
   always @(posedge clk)
-    \core_bigendian_i$10  <= \core_bigendian_i$10$next ;
+    \core_bigendian_i$3  <= \core_bigendian_i$3$next ;
   always @(posedge clk)
     core_core_core_cia <= \core_core_core_cia$next ;
   always @(posedge clk)
@@ -212373,21 +212373,21 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   always @(posedge clk)
     core_core_core_traptype <= \core_core_core_traptype$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal  <= \core_core_core_exc_$signal$next ;
+    core_core_core_exc_alignment <= \core_core_core_exc_alignment$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$3  <= \core_core_core_exc_$signal$3$next ;
+    core_core_core_exc_instr_fault <= \core_core_core_exc_instr_fault$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$4  <= \core_core_core_exc_$signal$4$next ;
+    core_core_core_exc_invalid <= \core_core_core_exc_invalid$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$5  <= \core_core_core_exc_$signal$5$next ;
+    core_core_core_exc_badtree <= \core_core_core_exc_badtree$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$6  <= \core_core_core_exc_$signal$6$next ;
+    core_core_core_exc_perm_error <= \core_core_core_exc_perm_error$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$7  <= \core_core_core_exc_$signal$7$next ;
+    core_core_core_exc_rc_error <= \core_core_core_exc_rc_error$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$8  <= \core_core_core_exc_$signal$8$next ;
+    core_core_core_exc_segment_fault <= \core_core_core_exc_segment_fault$next ;
   always @(posedge clk)
-    \core_core_core_exc_$signal$9  <= \core_core_core_exc_$signal$9$next ;
+    core_core_core_exc_happened <= \core_core_core_exc_happened$next ;
   always @(posedge clk)
     core_core_pc <= \core_core_pc$next ;
   always @(posedge clk)
@@ -212433,7 +212433,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   always @(posedge clk)
     dec2_cur_msr <= \dec2_cur_msr$next ;
   core core (
-    .bigendian_i(\core_bigendian_i$10 ),
+    .bigendian_i(\core_bigendian_i$3 ),
     .cia__data_o(core_cia__data_o),
     .cia__ren(core_cia__ren),
     .core_core__SV_Ptype(core_core_core__SV_Ptype),
@@ -212444,14 +212444,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .core_core_cr_rd(core_core_core_cr_rd),
     .core_core_cr_rd_ok(core_core_core_cr_rd_ok),
     .core_core_cr_wr(core_core_core_cr_wr),
-    .\core_core_exc_$signal (\core_core_core_exc_$signal ),
-    .\core_core_exc_$signal$3 (\core_core_core_exc_$signal$3 ),
-    .\core_core_exc_$signal$4 (\core_core_core_exc_$signal$4 ),
-    .\core_core_exc_$signal$5 (\core_core_core_exc_$signal$5 ),
-    .\core_core_exc_$signal$6 (\core_core_core_exc_$signal$6 ),
-    .\core_core_exc_$signal$7 (\core_core_core_exc_$signal$7 ),
-    .\core_core_exc_$signal$8 (\core_core_core_exc_$signal$8 ),
-    .\core_core_exc_$signal$9 (\core_core_core_exc_$signal$9 ),
+    .core_core_exc_alignment(core_core_core_exc_alignment),
+    .core_core_exc_badtree(core_core_core_exc_badtree),
+    .core_core_exc_happened(core_core_core_exc_happened),
+    .core_core_exc_instr_fault(core_core_core_exc_instr_fault),
+    .core_core_exc_invalid(core_core_core_exc_invalid),
+    .core_core_exc_perm_error(core_core_core_exc_perm_error),
+    .core_core_exc_rc_error(core_core_core_exc_rc_error),
+    .core_core_exc_segment_fault(core_core_core_exc_segment_fault),
     .core_core_fn_unit(core_core_core_fn_unit),
     .core_core_input_carry(core_core_core_input_carry),
     .core_core_insn(core_core_core_insn),
@@ -212504,7 +212504,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .cu_st__go_i(core_cu_st__go_i),
     .cu_st__rel_o(core_cu_st__rel_o),
     .data_i(core_data_i),
-    .\data_i$11 (\core_data_i$12 ),
+    .\data_i$4 (\core_data_i$5 ),
     .dbus__ack(dbus__ack),
     .dbus__adr(dbus__adr),
     .dbus__cyc(dbus__cyc),
@@ -212517,13 +212517,13 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .dmi__addr(core_dmi__addr),
     .dmi__data_o(core_dmi__data_o),
     .dmi__ren(core_dmi__ren),
-    .\exc_o_$signal (\core_exc_o_$signal ),
+    .exc_o_happened(core_exc_o_happened),
     .full_rd2__data_o(core_full_rd2__data_o),
     .full_rd2__ren(core_full_rd2__ren),
     .full_rd__data_o(core_full_rd__data_o),
     .full_rd__ren(core_full_rd__ren),
     .issue__addr(core_issue__addr),
-    .\issue__addr$12 (\core_issue__addr$13 ),
+    .\issue__addr$5 (\core_issue__addr$6 ),
     .issue__data_i(core_issue__data_i),
     .issue__data_o(core_issue__data_o),
     .issue__ren(core_issue__ren),
@@ -212538,7 +212538,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .sv__ren(core_sv__ren),
     .wb_dcache_en(core_wb_dcache_en),
     .wen(core_wen),
-    .\wen$10 (\core_wen$11 )
+    .\wen$3 (\core_wen$4 )
   );
   dbg dbg (
     .clk(clk),
@@ -212580,9 +212580,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .cr_in1(dec2_cr_in1),
     .cr_in1_ok(dec2_cr_in1_ok),
     .cr_in2(dec2_cr_in2),
-    .\cr_in2$1 (\dec2_cr_in2$14 ),
+    .\cr_in2$1 (\dec2_cr_in2$7 ),
     .cr_in2_ok(dec2_cr_in2_ok),
-    .\cr_in2_ok$2 (\dec2_cr_in2_ok$15 ),
+    .\cr_in2_ok$2 (\dec2_cr_in2_ok$8 ),
     .cr_out(dec2_cr_out),
     .cr_out_ok(dec2_cr_out_ok),
     .cr_rd(dec2_cr_rd),
@@ -212601,14 +212601,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     .cur_pc(dec2_cur_pc),
     .ea(dec2_ea),
     .ea_ok(dec2_ea_ok),
-    .\exc_$signal (\dec2_exc_$signal ),
-    .\exc_$signal$3 (\dec2_exc_$signal$16 ),
-    .\exc_$signal$4 (\dec2_exc_$signal$17 ),
-    .\exc_$signal$5 (\dec2_exc_$signal$18 ),
-    .\exc_$signal$6 (\dec2_exc_$signal$19 ),
-    .\exc_$signal$7 (\dec2_exc_$signal$20 ),
-    .\exc_$signal$8 (\dec2_exc_$signal$21 ),
-    .\exc_$signal$9 (\dec2_exc_$signal$22 ),
+    .exc_alignment(dec2_exc_alignment),
+    .exc_badtree(dec2_exc_badtree),
+    .exc_happened(dec2_exc_happened),
+    .exc_instr_fault(dec2_exc_instr_fault),
+    .exc_invalid(dec2_exc_invalid),
+    .exc_perm_error(dec2_exc_perm_error),
+    .exc_rc_error(dec2_exc_rc_error),
+    .exc_segment_fault(dec2_exc_segment_fault),
     .fast1(dec2_fast1),
     .fast1_ok(dec2_fast1_ok),
     .fast2(dec2_fast2),
@@ -213059,10 +213059,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     \delay$next  = delay;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
-    casez (\$25 )
+    casez (\$11 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */
       1'h1:
-          \delay$next  = \$27 [1:0];
+          \delay$next  = \$13 [1:0];
     endcase
   end
   always @* begin
@@ -213159,7 +213159,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   end
   always @* begin
     if (\initial ) begin end
-    \core_bigendian_i$10$next  = \core_bigendian_i$10 ;
+    \core_bigendian_i$3$next  = \core_bigendian_i$3 ;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
     casez (issue_fsm_state)
       /* \nmigen.decoding  = "ISSUE_START/0" */
@@ -213185,12 +213185,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "DECODE_SV/2" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
       3'h2:
-          \core_bigendian_i$10$next  = core_bigendian_i;
+          \core_bigendian_i$3$next  = core_bigendian_i;
     endcase
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (rst)
       1'h1:
-          \core_bigendian_i$10$next  = 1'h0;
+          \core_bigendian_i$3$next  = 1'h0;
     endcase
   end
   always @* begin
@@ -213266,7 +213266,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
       3'h7:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$246 )
+          casez (\$232 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 exec_pc_ready_i = 1'h1;
@@ -213311,36 +213311,36 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
       3'h7:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$252 )
+          casez (\$238 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
                 casez (exec_pc_valid_o)
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
                   1'h1:
-                      is_last = \$254 ;
+                      is_last = \$240 ;
                 endcase
           endcase
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \core_wen$11  = 3'h0;
+    \core_wen$4  = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *)
     casez (update_svstate)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */
       1'h1:
-          \core_wen$11  = 3'h4;
+          \core_wen$4  = 3'h4;
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \core_data_i$12  = 64'h0000000000000000;
+    \core_data_i$5  = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *)
     casez (update_svstate)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */
       1'h1:
-          \core_data_i$12  = \$256 ;
+          \core_data_i$5  = \$242 ;
     endcase
   end
   always @* begin
@@ -213373,7 +213373,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *)
-          casez (\$258 )
+          casez (\$244 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
             1'h1:
                 core_ivalid_i = 1'h1;
@@ -213415,7 +213415,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-          casez (\$260 )
+          casez (\$246 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *)
@@ -213446,7 +213446,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-          casez (\$262 )
+          casez (\$248 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
             1'h1:
                 exec_pc_valid_o = 1'h1;
@@ -213528,7 +213528,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     casez (d_cr_delay)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */
       1'h1:
-          dbg_d_cr_data = \$264 ;
+          dbg_d_cr_data = \$250 ;
     endcase
   end
   always @* begin
@@ -213567,7 +213567,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     casez (d_xer_delay)
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */
       1'h1:
-          dbg_d_xer_data = \$266 ;
+          dbg_d_xer_data = \$252 ;
     endcase
   end
   always @* begin
@@ -213658,12 +213658,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "DEC_WRITE/1" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
       2'h1:
-          new_dec = \$268 [63:0];
+          new_dec = \$254 [63:0];
     endcase
   end
   always @* begin
     if (\initial ) begin end
-    \core_issue__addr$13  = 4'h0;
+    \core_issue__addr$6  = 4'h0;
     (* full_case = 32'd1 *)
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *)
     casez (fsm_state)
@@ -213674,7 +213674,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "DEC_WRITE/1" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */
       2'h1:
-          \core_issue__addr$13  = 4'h6;
+          \core_issue__addr$6  = 4'h6;
       /* \nmigen.decoding  = "TB_READ/2" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */
       2'h2:
@@ -213682,7 +213682,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "TB_WRITE/3" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
       2'h3:
-          \core_issue__addr$13  = 4'h7;
+          \core_issue__addr$6  = 4'h7;
     endcase
   end
   always @* begin
@@ -213754,7 +213754,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "TB_WRITE/3" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */
       2'h3:
-          new_tb = \$271 [63:0];
+          new_tb = \$257 [63:0];
     endcase
   end
   always @* begin
@@ -213802,7 +213802,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
       2'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
-          casez (\$23 )
+          casez (\$9 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */
             1'h1:
                 \dec2_cur_msr$next  = core_msr__data_o;
@@ -213855,10 +213855,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     \pc_ok_delay$next  = pc_ok_delay;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$40 )
+    casez (\$26 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
-          \pc_ok_delay$next  = \$42 ;
+          \pc_ok_delay$next  = \$28 ;
     endcase
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (rst)
@@ -213870,7 +213870,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     pc = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$44 )
+    casez (\$30 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
         begin
@@ -213893,7 +213893,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     core_cia__ren = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$46 )
+    casez (\$32 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
           (* full_case = 32'd1 *)
@@ -213912,10 +213912,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     \svstate_ok_delay$next  = svstate_ok_delay;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$48 )
+    casez (\$34 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
-          \svstate_ok_delay$next  = \$50 ;
+          \svstate_ok_delay$next  = \$36 ;
     endcase
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (rst)
@@ -213927,7 +213927,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     svstate = 64'h0000000000000000;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$52 )
+    casez (\$38 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
         begin
@@ -213935,7 +213935,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
           casez (svstate_i_ok)
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */
             1'h1:
-                svstate = \$54 ;
+                svstate = \$40 ;
           endcase
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" *)
           casez (svstate_ok_delay)
@@ -213950,7 +213950,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     if (\initial ) begin end
     core_sv__ren = 3'h0;
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
-    casez (\$56 )
+    casez (\$42 )
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */
       1'h1:
           (* full_case = 32'd1 *)
@@ -213976,7 +213976,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$62 )
+          casez (\$48 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -213997,7 +213997,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-                casez (\$66 )
+                casez (\$52 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
                   1'h1:
                       core_wen = 3'h1;
@@ -214028,7 +214028,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$72 )
+          casez (\$58 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
@@ -214036,7 +214036,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
                   1'h1:
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-                      casez ({ \$78 , \$74  })
+                      casez ({ \$64 , \$60  })
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
                         2'b?1:
                             /* empty */;
@@ -214076,7 +214076,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$84 )
+          casez (\$70 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214097,7 +214097,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-                casez (\$88 )
+                casez (\$74 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
                   1'h1:
                       core_data_i = nia;
@@ -214128,7 +214128,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$94 )
+          casez (\$80 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
@@ -214136,7 +214136,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */
                   1'h1:
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-                      casez ({ \$100 , \$96  })
+                      casez ({ \$86 , \$82  })
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
                         2'b?1:
                             /* empty */;
@@ -214294,7 +214294,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */
       2'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *)
-          casez (\$102 )
+          casez (\$88 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */
             1'h1:
                 \msr_read$next  = 1'h1;
@@ -214383,7 +214383,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                 /* empty */;
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */
             default:
-                \nia$next  = \$104 [63:0];
+                \nia$next  = \$90 [63:0];
           endcase
     endcase
     (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *)
@@ -214418,7 +214418,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                 /* empty */;
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */
             default:
-                \dec2_raw_opcode_in$next  = \$107 ;
+                \dec2_raw_opcode_in$next  = \$93 ;
           endcase
       /* \nmigen.decoding  = "INSN_READ2/3" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */
@@ -214431,7 +214431,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                 /* empty */;
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
             default:
-                \dec2_raw_opcode_in$next  = \$111 ;
+                \dec2_raw_opcode_in$next  = \$97 ;
           endcase
     endcase
   end
@@ -214470,7 +214470,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$122 )
+          casez (\$108 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214512,7 +214512,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$128 )
+          casez (\$114 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
@@ -214521,7 +214521,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                   1'h1:
                       (* full_case = 32'd1 *)
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-                      casez ({ \$134 , \$130  })
+                      casez ({ \$120 , \$116  })
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
                         2'b?1:
                             /* empty */;
@@ -214559,7 +214559,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
       3'h0:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$148 )
+          casez (\$134 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 fetch_pc_valid_i = 1'h1;
@@ -214576,7 +214576,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
       3'h0:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$154 )
+          casez (\$140 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" *)
@@ -214595,7 +214595,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
             1'h1:
                 (* full_case = 32'd1 *)
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-                casez (\$158 )
+                casez (\$144 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
                   1'h1:
                       \issue_fsm_state$next  = 3'h0;
@@ -214626,7 +214626,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */
       3'h5:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *)
-          casez (\$160 )
+          casez (\$146 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
             1'h1:
                 \issue_fsm_state$next  = 3'h2;
@@ -214648,7 +214648,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
       3'h7:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$166 )
+          casez (\$152 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
@@ -214657,7 +214657,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                   1'h1:
                       (* full_case = 32'd1 *)
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-                      casez ({ \$172 , \$168  })
+                      casez ({ \$158 , \$154  })
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
                         2'b?1:
                             \issue_fsm_state$next  = 3'h0;
@@ -214688,7 +214688,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$178 )
+          casez (\$164 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214725,7 +214725,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$184 )
+          casez (\$170 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 /* empty */;
@@ -214746,7 +214746,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$190 )
+          casez (\$176 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214788,7 +214788,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$196 )
+          casez (\$182 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 /* empty */;
@@ -214818,7 +214818,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
-          casez (\$198 )
+          casez (\$184 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" */
             1'h1:
                 \pc_changed$next  = 1'h1;
@@ -214841,7 +214841,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$206 )
+          casez (\$192 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214883,7 +214883,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$212 )
+          casez (\$198 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *)
@@ -214892,7 +214892,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
                   1'h1:
                       (* full_case = 32'd1 *)
                       (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
-                      casez ({ \$218 , \$214  })
+                      casez ({ \$204 , \$200  })
                         /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */
                         2'b?1:
                             /* empty */;
@@ -214926,7 +214926,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h0:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *)
-          casez (\$224 )
+          casez (\$210 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */
             1'h1:
                 /* empty */;
@@ -214968,7 +214968,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       3'h7:
           (* full_case = 32'd1 *)
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *)
-          casez (\$230 )
+          casez (\$216 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */
             1'h1:
                 /* empty */;
@@ -214998,7 +214998,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *)
-          casez (\$232 )
+          casez (\$218 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" */
             1'h1:
                 \sv_changed$next  = 1'h1;
@@ -215042,7 +215042,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
-                casez (\$238 )
+                casez (\$224 )
                   /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
                   1'h1:
                       insn_done = 1'h1;
@@ -215060,7 +215060,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */
       1'h1:
           (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *)
-          casez (\$240 )
+          casez (\$226 )
             /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */
             1'h1:
                 (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *)
@@ -215170,14 +215170,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
     \core_core_core_oe_ok$next  = core_core_core_oe_ok;
     \core_core_core_input_carry$next  = core_core_core_input_carry;
     \core_core_core_traptype$next  = core_core_core_traptype;
-    \core_core_core_exc_$signal$next  = \core_core_core_exc_$signal ;
-    \core_core_core_exc_$signal$3$next  = \core_core_core_exc_$signal$3 ;
-    \core_core_core_exc_$signal$4$next  = \core_core_core_exc_$signal$4 ;
-    \core_core_core_exc_$signal$5$next  = \core_core_core_exc_$signal$5 ;
-    \core_core_core_exc_$signal$6$next  = \core_core_core_exc_$signal$6 ;
-    \core_core_core_exc_$signal$7$next  = \core_core_core_exc_$signal$7 ;
-    \core_core_core_exc_$signal$8$next  = \core_core_core_exc_$signal$8 ;
-    \core_core_core_exc_$signal$9$next  = \core_core_core_exc_$signal$9 ;
+    \core_core_core_exc_alignment$next  = core_core_core_exc_alignment;
+    \core_core_core_exc_instr_fault$next  = core_core_core_exc_instr_fault;
+    \core_core_core_exc_invalid$next  = core_core_core_exc_invalid;
+    \core_core_core_exc_badtree$next  = core_core_core_exc_badtree;
+    \core_core_core_exc_perm_error$next  = core_core_core_exc_perm_error;
+    \core_core_core_exc_rc_error$next  = core_core_core_exc_rc_error;
+    \core_core_core_exc_segment_fault$next  = core_core_core_exc_segment_fault;
+    \core_core_core_exc_happened$next  = core_core_core_exc_happened;
     \core_core_core_trapaddr$next  = core_core_core_trapaddr;
     \core_core_core_cr_rd$next  = core_core_core_cr_rd;
     \core_core_core_cr_rd_ok$next  = core_core_core_cr_rd_ok;
@@ -215209,7 +215209,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
       /* \nmigen.decoding  = "DECODE_SV/2" */
       /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */
       3'h2:
-          { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next  } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
+          { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_happened$next , \core_core_core_exc_segment_fault$next , \core_core_core_exc_rc_error$next , \core_core_core_exc_perm_error$next , \core_core_core_exc_badtree$next , \core_core_core_exc_invalid$next , \core_core_core_exc_instr_fault$next , \core_core_core_exc_alignment$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next  } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment, dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$8 , \dec2_cr_in2$7 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
     endcase
     (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
     casez (rst)
@@ -215238,34 +215238,34 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
           \core_core_core__SV_Ptype$next  = 2'h0;
           \core_core_core_rc_ok$next  = 1'h0;
           \core_core_core_oe_ok$next  = 1'h0;
-          \core_core_core_exc_$signal$next  = 1'h0;
-          \core_core_core_exc_$signal$3$next  = 1'h0;
-          \core_core_core_exc_$signal$4$next  = 1'h0;
-          \core_core_core_exc_$signal$5$next  = 1'h0;
-          \core_core_core_exc_$signal$6$next  = 1'h0;
-          \core_core_core_exc_$signal$7$next  = 1'h0;
-          \core_core_core_exc_$signal$8$next  = 1'h0;
-          \core_core_core_exc_$signal$9$next  = 1'h0;
+          \core_core_core_exc_alignment$next  = 1'h0;
+          \core_core_core_exc_instr_fault$next  = 1'h0;
+          \core_core_core_exc_invalid$next  = 1'h0;
+          \core_core_core_exc_badtree$next  = 1'h0;
+          \core_core_core_exc_perm_error$next  = 1'h0;
+          \core_core_core_exc_rc_error$next  = 1'h0;
+          \core_core_core_exc_segment_fault$next  = 1'h0;
+          \core_core_core_exc_happened$next  = 1'h0;
           \core_core_core_cr_rd_ok$next  = 1'h0;
           \core_core_cr_wr_ok$next  = 1'h0;
         end
     endcase
   end
-  assign \$27  = \$28 ;
-  assign \$104  = \$105 ;
-  assign \$112  = \$113 ;
-  assign \$136  = \$137 ;
-  assign \$139  = \$140 ;
-  assign \$268  = \$269 ;
-  assign \$271  = \$272 ;
+  assign \$13  = \$14 ;
+  assign \$90  = \$91 ;
+  assign \$98  = \$99 ;
+  assign \$122  = \$123 ;
+  assign \$125  = \$126 ;
+  assign \$254  = \$255 ;
+  assign \$257  = \$258 ;
   assign svstate_i_ok = 1'h0;
   assign svstate_i = 32'd0;
   assign is_svp64_mode = 1'h0;
   assign pred_insn_ready_o = 1'h0;
   assign pred_mask_valid_o = 1'h0;
-  assign exc_happened = \$142 ;
-  assign next_dststep = \$140 [6:0];
-  assign next_srcstep = \$137 [6:0];
+  assign exc_happened = \$128 ;
+  assign next_dststep = \$126 [6:0];
+  assign next_srcstep = \$123 [6:0];
   assign dbg_core_dbg_msr = dec2_cur_msr;
   assign { dbg_core_dbg_core_dbg_maxvl, dbg_core_dbg_core_dbg_vl, dbg_core_dbg_core_dbg_srcstep, dbg_core_dbg_core_dbg_dststep, dbg_core_dbg_core_dbg_subvl, dbg_core_dbg_core_dbg_svstep } = svstate[31:0];
   assign dbg_core_dbg_pc = pc;
@@ -215273,12 +215273,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus
   assign pc_o = dec2_cur_pc;
   assign core_cu_st__go_i = cu_st__rel_o_rise;
   assign core_cu_ad__go_i = core_cu_ad__rel_o;
-  assign cu_st__rel_o_rise = \$38 ;
+  assign cu_st__rel_o_rise = \$24 ;
   assign \cu_st__rel_o_dly$next  = core_cu_st__rel_o;
   assign dec2_bigendian = core_bigendian_i;
   assign busy_o = core_corebusy_o;
   assign core_coresync_rst = ti_rst;
-  assign ti_rst = \$34 ;
+  assign ti_rst = \$20 ;
   assign por_clk = clk;
   assign { xics_icp_ics_i_pri, xics_icp_ics_i_src } = { xics_ics_icp_o_pri, xics_ics_icp_o_src };
   assign sram4k_3_enable = jtag_wb_sram_en;
@@ -216840,7 +216840,7 @@ module wrappll(clk_24_i, pll_test_o, clk_sel_i, pll_vco_o, clk_pll_o);
   output pll_test_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
   output pll_vco_o;
-  pll pll (
+  pll real_pll (
     .a0(clk_sel_i[0]),
     .a1(clk_sel_i[1]),
     .div_out_test(pll_test_o),
-- 
2.30.2