From 7903468828570161671ebfcb82c489d2f2e0644e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 7 Apr 2022 11:56:48 +0100 Subject: [PATCH] code-comments --- src/nmigen_gf/hdl/cldivrem.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py index 43257e7..07e6e34 100644 --- a/src/nmigen_gf/hdl/cldivrem.py +++ b/src/nmigen_gf/hdl/cldivrem.py @@ -96,10 +96,12 @@ class EqualLeadingZeroCount(Elaboratable): # OR-in both_ones m.d.comb += addend2.eq(~different) + # now [ab]use add: the last bit [carry-out] is the result csum = Signal(self.width + 1) carry_in = 1 # both have no leading zeros so far, so set carry m.d.comb += csum.eq(addend1 + addend2 + carry_in) m.d.comb += self.out.eq(csum[self.width]) # out is carry-out + return m # TODO: add CLDivRem -- 2.30.2