From 7df8f1a16741a6f9bc42a7a39aa33ecb6e6fd957 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 11:39:10 +0100 Subject: [PATCH] rename variable wid -> dep --- src/scoreboard/global_pending.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py index f8ab4015..e3bcb555 100644 --- a/src/scoreboard/global_pending.py +++ b/src/scoreboard/global_pending.py @@ -33,13 +33,13 @@ class GlobalPending(Elaboratable): for v in fu_vecs: assert len(v) == dep, "FU Vector must be same width as regfile" - self.g_pend_o = Signal(wid, reset_less=True) # global pending vector + self.g_pend_o = Signal(dep, reset_less=True) # global pending vector def elaborate(self, platform): m = Module() pend_l = [] - for i in range(self.reg_width): # per-register + for i in range(self.reg_dep): # per-register vec_bit_l = [] for v in self.fu_vecs: vec_bit_l.append(v[i]) # fu bit for same register -- 2.30.2