From 7f9016c7d485eabd6d68756e3c3bbf68ff71c178 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 19:07:40 +0100
Subject: [PATCH] disallow adding verilog files

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 3a8cbad..ff14265 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 __pycache__/
 sim_build_*/
 results_*.xml
+*.v
-- 
2.30.2