From 8a966e2e6771ca5b207db618319f96e841dd63fe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 21 Feb 2022 18:41:09 +0000 Subject: [PATCH] add a debug verilog dump of one of the FakePHY SocTest cases to see what is going on --- gram/test/test_soc.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index ceb8f66..8187b3f 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -7,6 +7,7 @@ from nmigen import * from nmigen.asserts import Assert, Assume from nmigen_soc import wishbone, memory from nmigen.lib.cdc import ResetSynchronizer +from nmigen.cli import verilog from lambdasoc.periph import Peripheral from lambdasoc.soc.base import SoC @@ -141,6 +142,10 @@ class SocTestCase(FHDLTestCase): dramcore_addr=0x00000000, ddr_addr=0x10000000) + vl = verilog.convert(soc, ports=None) + with open("test_soc_multiple_reads.v", "w") as f: + f.write(vl) + def process(): yield from SocTestCase.init_seq(soc.bus) -- 2.30.2