From 8d0df76b5f5afa39167889bb49ef7bec22590f95 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jan 2022 12:37:25 +0000 Subject: [PATCH] alias Display to D - shorter --- sim.py | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/sim.py b/sim.py index 47c7684..44fcf1b 100755 --- a/sim.py +++ b/sim.py @@ -301,43 +301,43 @@ class LibreSoCSim(SoCSDRAM): # debug messages out self.sync += If(dbg_msg, (If(active_dbg & (dbg_addr == 0b10), # PC - Display("pc : %016x", dbg_dout), + D("pc : %016x", dbg_dout), ), If(dbg_addr == 0b10, # PC pc.eq(dbg_dout), # capture PC ), If(dbg_addr == 0b11, # MSR - Display(" msr: %016x", dbg_dout), + D(" msr: %016x", dbg_dout), ), If(dbg_addr == 0b1000, # CR - Display(" cr : %016x", dbg_dout), + D(" cr : %016x", dbg_dout), ), If(dbg_addr == 0b1001, # XER - Display(" xer: so %d ca %d 32 %d ov %d 32 %d", + D(" xer: so %d ca %d 32 %d ov %d 32 %d", xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32), ), If(dbg_addr == 0b101, # GPRs (and "fast" SPRs) - If(regnum <= 31, Display(" gpr%02x: %016x", + If(regnum <= 31, D(" gpr%02x: %016x", regnum, dbg_dout),), # GPRs - If(regnum == 32, Display(" LR: %016x", dbg_dout),), # LR - If(regnum == 33, Display(" CTR: %016x", dbg_dout),), # CTR - If(regnum == 34, Display(" SRR0: %016x", dbg_dout),), # SRR0 - If(regnum == 35, Display(" SRR1: %016x", dbg_dout),), # SRR1 - If(regnum == 36, Display(" HSRR0: %016x", dbg_dout),), # HSRR0 - If(regnum == 37, Display(" HSRR1: %016x", dbg_dout),), # HSRR1 - If(regnum == 38, Display(" SPRG0: %016x", dbg_dout),), # SPRG0 - If(regnum == 39, Display(" SPRG1: %016x", dbg_dout),), # SPRG1 - If(regnum == 40, Display(" SPRG2: %016x", dbg_dout),), # SPRG2 - If(regnum == 41, Display(" SPRG3: %016x", dbg_dout),), # SPRG3 - If(regnum == 42, Display(" HSPRG0: %016x", dbg_dout),), # HSPRG0 - If(regnum == 43, Display(" HSPRG1: %016x", dbg_dout),), # HSPRG1 - If(regnum == 44, Display(" XER: %016x", dbg_dout),), # XER - If(regnum == 45, Display(" TAR: %016x", dbg_dout),), # TAR - #If(regnum == 46, Display(" SVSRR0: %016x", dbg_dout),), # SVSRR0 + If(regnum == 32, D(" LR: %016x", dbg_dout),), # LR + If(regnum == 33, D(" CTR: %016x", dbg_dout),), # CTR + If(regnum == 34, D(" SRR0: %016x", dbg_dout),), # SRR0 + If(regnum == 35, D(" SRR1: %016x", dbg_dout),), # SRR1 + If(regnum == 36, D(" HSRR0: %016x", dbg_dout),), # HSRR0 + If(regnum == 37, D(" HSRR1: %016x", dbg_dout),), # HSRR1 + If(regnum == 38, D(" SPRG0: %016x", dbg_dout),), # SPRG0 + If(regnum == 39, D(" SPRG1: %016x", dbg_dout),), # SPRG1 + If(regnum == 40, D(" SPRG2: %016x", dbg_dout),), # SPRG2 + If(regnum == 41, D(" SPRG3: %016x", dbg_dout),), # SPRG3 + If(regnum == 42, D(" HSPRG0: %016x", dbg_dout),), # HSPRG0 + If(regnum == 43, D(" HSPRG1: %016x", dbg_dout),), # HSPRG1 + If(regnum == 44, D(" XER: %016x", dbg_dout),), # XER + If(regnum == 45, D(" TAR: %016x", dbg_dout),), # TAR + #If(regnum == 46, D(" SVSRR0: %016x", dbg_dout),), # SVSRR0 ), # also check if this is a "stat" If(dbg_addr == 1, # requested a STAT - #Display(" stat: %x", dbg_dout), + #D(" stat: %x", dbg_dout), If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode dmirunning.eq(1), # continue running dmi_monitor.eq(0), # and stop monitor mode @@ -443,7 +443,7 @@ class LibreSoCSim(SoCSDRAM): # monitor bbus read/write self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack, - Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x", + D(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x", #uptime, 0, self.cpu.dbus.adr, @@ -459,7 +459,7 @@ class LibreSoCSim(SoCSDRAM): # monitor ibus write self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack & self.cpu.ibus.we, - Display(" [%06x] iadr: %8x, s %01x w %016x", + D(" [%06x] iadr: %8x, s %01x w %016x", #uptime, 0, self.cpu.ibus.adr, @@ -470,7 +470,7 @@ class LibreSoCSim(SoCSDRAM): # monitor ibus read self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack & ~self.cpu.ibus.we, - Display(" [%06x] iadr: %8x, s %01x r %016x", + D(" [%06x] iadr: %8x, s %01x r %016x", #uptime, 0, self.cpu.ibus.adr, -- 2.30.2