From 9e07623b6159192d604d3225aef81c994c7d503a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jul 2020 11:06:09 +0200 Subject: [PATCH] integration/soc: fix dma_bus typo. --- litex/soc/integration/soc.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 20025383..477d883a 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -922,7 +922,7 @@ class SoC(Module): if ((len(self.dma_bus.masters) == 1) and (len(self.dma_bus.slaves) == 1) and (next(iter(self.dma_bus.regions.values())).origin == 0)): - self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint( + self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint( master = next(iter(self.dma_bus.masters.values())), slave = next(iter(self.dma_bus.slaves.values()))) # Otherwise, use InterconnectShared. @@ -931,10 +931,10 @@ class SoC(Module): masters = self.dma_bus.masters.values(), slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()], register = True) - self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format( - colorer(self.dma_bus_interconnect.__class__.__name__), - colorer(len(self.dma_bus.masters)), - colorer(len(self.dma_bus.slaves)))) + self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format( + colorer(self.dma_bus_interconnect.__class__.__name__), + colorer(len(self.dma_bus.masters)), + colorer(len(self.dma_bus.slaves)))) self.add_constant("CONFIG_CPU_HAS_DMA_BUS") # SoC CSR Interconnect --------------------------------------------------------------------- -- 2.30.2