From a298ae5ded7672c5c913d1f1ef044a4b38bd0dfe Mon Sep 17 00:00:00 2001 From: Aleksandar Kostovic Date: Fri, 12 Apr 2019 22:23:25 +0200 Subject: [PATCH] Create fsqrt.py file and put the verilog code in comments to indicate the basic structure of algorithm --- src/add/fsqrt.py | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 src/add/fsqrt.py diff --git a/src/add/fsqrt.py b/src/add/fsqrt.py new file mode 100644 index 00000000..6b233779 --- /dev/null +++ b/src/add/fsqrt.py @@ -0,0 +1,43 @@ + + +""" +//This is the main code of integer sqrt function found here:http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html +// + +module testbench; + +reg [15:0] sqr; + +//Verilog function to find square root of a 32 bit number. +//The output is 16 bit. +function [15:0] sqrt; + input [31:0] num; //declare input + //intermediate signals. + reg [31:0] a; + reg [15:0] q; + reg [17:0] left,right,r; + integer i; +begin + //initialize all the variables. + a = num; + q = 0; + i = 0; + left = 0; //input to adder/sub + right = 0; //input to adder/sub + r = 0; //remainder + //run the calculations for 16 iterations. + for(i=0;i<16;i=i+1) begin + right = {q,r[17],1'b1}; + left = {r[15:0],a[31:30]}; + a = {a[29:0],2'b00}; //left shift by 2 bits. + if (r[17] == 1) //add if r is negative + r = left + right; + else //subtract if r is positive + r = left - right; + q = {q[14:0],!r[17]}; + end + sqrt = q; //final assignment of output. +end +endfunction //end of Function + +""" -- 2.30.2