From a69de0b0882e35feda82b050859dd9ba718c7188 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 May 2019 06:02:39 +0100
Subject: [PATCH] got fpmul working (potential bug in softfloat NaN handling)

---
 src/ieee754/fpcommon/postnormalise.py | 10 +++++-----
 src/ieee754/fpmul/specialcases.py     |  2 +-
 src/ieee754/fpmul/test/test_mul.py    | 11 +++++++----
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py
index 4ab6639c..4ef879e3 100644
--- a/src/ieee754/fpcommon/postnormalise.py
+++ b/src/ieee754/fpcommon/postnormalise.py
@@ -16,7 +16,7 @@ from .postcalc import FPAddStage1Data
 class FPNorm1Data:
 
     def __init__(self, width, id_wid):
-        self.roundz = Signal(reset_less=True)
+        self.roundz = Signal(reset_less=True, name="norm1_roundz")
         self.z = FPNumBase(width, False)
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
@@ -120,11 +120,11 @@ class FPNorm1ModSingle(Elaboratable):
                     msr.inp.eq(temp_m),
                     msr.diff.eq(ediff_n126),
                     self.o.z.m.eq(msr.m[3:]),
-                    of.m0.eq(temp_s[3]),   # copy of mantissa[0]
+                    of.m0.eq(msr.m[3]),   # copy of mantissa[0]
                     # overflow in bits 0..1: got shifted too (leave sticky)
-                    of.guard.eq(temp_s[2]),     # guard
-                    of.round_bit.eq(temp_s[1]), # round
-                    of.sticky.eq(temp_s[0]),    # sticky
+                    of.guard.eq(msr.m[2]),     # guard
+                    of.round_bit.eq(msr.m[1]), # round
+                    of.sticky.eq(msr.m[0]),    # sticky
                     self.o.z.e.eq(i.z.e + ediff_n126),
                 ]
 
diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index 57b6f168..83f82558 100644
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -56,7 +56,7 @@ class FPMulSpecialCasesMod(Elaboratable):
                     ]
 
         obz = Signal(reset_less=True)
-        m.d.comb += obz.eq(a1.is_zero & b1.is_zero)
+        m.d.comb += obz.eq(a1.is_zero | b1.is_zero)
 
         sabx = Signal(reset_less=True)   # sign a xor b (sabx, get it?)
         m.d.comb += sabx.eq(a1.s ^ b1.s)
diff --git a/src/ieee754/fpmul/test/test_mul.py b/src/ieee754/fpmul/test/test_mul.py
index 72ec4a0a..ea655109 100644
--- a/src/ieee754/fpmul/test/test_mul.py
+++ b/src/ieee754/fpmul/test/test_mul.py
@@ -16,16 +16,19 @@ from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,
 
 
 def tbench(dut, maxcount, num_loops):
-    yield from check_case(dut, 0x40000000, 0x40000000, 0x40800000)
-    yield from check_case(dut, 0x41400000, 0x40A00000, 0x42700000)
+
+    yield from check_case(dut, 0x40000000, 0x40000000, 0x40800000, 0xffcaeefa)
+    yield from check_case(dut, 0x41400000, 0x40A00000, 0x42700000, 0x3f803262)
 
     count = 0
 
     #regression tests
 
-    stimulus_a = [0xa4504d7, 0xba57711a, 0xbf9b1e94, 0x34082401, 0x5e8ef81,
+    stimulus_a = [0xffcaeefa, 0xae430313, 0xa4504d7,
+                  0xba57711a, 0xbf9b1e94, 0x34082401, 0x5e8ef81,
                   0x5c75da81, 0x2b017]
-    stimulus_b = [0xb4658540, 0xee1818c5, 0xc038ed3a, 0xb328cd45, 0x114f3db,
+    stimulus_b = [0x3f803262, 0x901c3214, 0xb4658540,
+                  0xee1818c5, 0xc038ed3a, 0xb328cd45, 0x114f3db,
                   0x2f642a39, 0xff3807ab]
     yield from run_fpunit(dut, stimulus_a, stimulus_b, mul, get_case)
     count += len(stimulus_a)
-- 
2.30.2