From a734fea8e80f9e99601b2ce8a109678f9b089db8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 6 Apr 2022 12:28:03 +0100 Subject: [PATCH] add QSPI support to arty_a7 --- src/ls2.py | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index b3b9e62..8cedbac 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -681,7 +681,8 @@ def build_platform(fpga, firmware): if platform is not None and \ fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']: # Override here to get FlashResource out of the way and enable Tercel - # direct access to the SPI flash + # direct access to the SPI flash. + # each pin needs a separate direction control spi_0_ios = [ Resource("spi_0", 0, Subsignal("dq0", Pins("W2", dir="io")), @@ -697,6 +698,22 @@ def build_platform(fpga, firmware): "dq2":1, "dq3": 1, "cs_n":0}) + if platform is not None and \ + fpga in ['arty_a7']: + # each pin needs a separate direction control + spi_0_ios = [ + Resource("spi_0", 0, + Subsignal("dq0", Pins("K17", dir="io")), + Subsignal("dq1", Pins("K18", dir="io")), + Subsignal("dq2", Pins("L14", dir="io")), + Subsignal("dq3", Pins("M14", dir="io")), + Subsignal("cs_n", Pins("L13", dir="o")), + Subsignal("clk", Pins("L16", dir="o")), + Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33")) + ] + platform.add_resources(spi_0_ios) + spi_0_pins = platform.request("spi_0", 0) + print ("spiflash pins", spi_0_pins) # Get Ethernet RMII resource pins -- 2.30.2