From a7d1f3e00c9e40ea2344ff23d5071d16d4211d28 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 6 Apr 2021 20:13:14 +0100 Subject: [PATCH] remove wb test from test.py --- ls180/pre_pnr/run_iverilog_ls180.sh | 2 +- ls180/pre_pnr/test.py | 141 ---------------------------- 2 files changed, 1 insertion(+), 142 deletions(-) diff --git a/ls180/pre_pnr/run_iverilog_ls180.sh b/ls180/pre_pnr/run_iverilog_ls180.sh index 1d5c42d..76db58e 100755 --- a/ls180/pre_pnr/run_iverilog_ls180.sh +++ b/ls180/pre_pnr/run_iverilog_ls180.sh @@ -13,7 +13,7 @@ make \ TOPLEVEL=$top \ COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \ COCOTB_HDL_TIMEUNIT=100ps \ - TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset,wishbone_basic" \ + TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset" \ SIM_BUILD=sim_build_iverilog_ls180 diff --git a/ls180/pre_pnr/test.py b/ls180/pre_pnr/test.py index 77a9958..dae23b5 100644 --- a/ls180/pre_pnr/test.py +++ b/ls180/pre_pnr/test.py @@ -285,147 +285,6 @@ def boundary_scan_reset(dut): wrap.info("IDCODE test completed") -@cocotb.test() -def boundary_scan_run(dut): - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - info = "Running boundary scan test; cpu running..." - wrap = yield from setup_sim(dut, info=info, clk_period=clk_period, - run=True) - jtag = yield from setup_jtag(wrap, tck_period = tck_period) - - yield from boundary_scan(wrap, jtag=jtag) - - wrap.info("IDCODE test completed") - - -@cocotb.test() -def wishbone_basic(dut): - """Test of an added Wishbone interface - - for this test the soc JTAG TAP address width is 29 bits and data is 64 - JTAG has access to the *full* memory range, including peripherals, - as defined by the litex setup. - """ - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - data_in = BinaryValue() - # these have to match with soc.debug.jtag.JTAG ircodes - cmd_MEMADDRESS = BinaryValue("0101") # 5 - cmd_MEMREAD = BinaryValue("0110") # 6 - cmd_MEMREADWRITE = BinaryValue("0111") # 7 - - info = "Running Wishbone basic test" - wrap = yield from setup_sim(dut, info=info, clk_period=clk_period, - run=False) - master = yield from setup_jtag(wrap, tck_period = tck_period) - - # Load the memory address - yield master.load_ir(cmd_MEMADDRESS) - dut._log.info("Loading address") - - # WBaddresses in soc.debug.jtag.JTAG are 29 bits - data_in.binstr = "00000000000000000000000000001" - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - - # Do write - yield master.load_ir(cmd_MEMREADWRITE) - dut._log.info("Writing memory") - - # data is 64-bit - data_in.binstr = "01010101" * 8 - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - - data_in.binstr = "10101010" * 8 - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - - # Load the memory address - yield master.load_ir(cmd_MEMADDRESS) - dut._log.info("Loading address") - - data_in.binstr = "00000000000000000000000000001" - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "00000000000000000000000000000" - - # Do read and write - yield master.load_ir(cmd_MEMREADWRITE) - dut._log.info("Reading and writing memory") - - data_in.binstr = "10101010" * 8 - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "01010101" * 8 - - data_in.binstr = "01010101" * 8 - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "10101010" * 8 - - # Load the memory address - yield master.load_ir(cmd_MEMADDRESS) - dut._log.info("Loading address") - - data_in.binstr = "00000000000000000000000000001" - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "00000000000000000000000000010" - - # Do read - yield master.load_ir(cmd_MEMREAD) - dut._log.info("Reading memory") - data_in.binstr = "00000000" * 8 - - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "10101010" * 8 - - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "01010101" * 8 - - # Load the memory address - yield master.load_ir(cmd_MEMADDRESS) # MEMADDR - dut._log.info("Loading address") - - data_in.binstr = "00000000000000000000000000001" - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "00000000000000000000000000010" - - # Do read - yield master.load_ir(cmd_MEMREAD) # MEMREAD - dut._log.info("Reading memory") - data_in.binstr = "00000000" * 8 - - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "10101010" * 8 - - dut._log.info(" input: {}".format(data_in.binstr)) - yield master.shift_data(data_in) - dut._log.info(" output: {}".format(master.result.binstr)) - assert master.result.binstr == "01010101" * 8 - - dut._log.info("{!r}".format(wbmem)) - - # demo / debug how to get boundary scan names. run "python3 test.py" if __name__ == '__main__': pinouts = get_jtag_boundary() -- 2.30.2