From aa538b61e229aad7ecceb0569a44bfd6bf54f06c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 Apr 2022 13:13:46 +0100 Subject: [PATCH] fix reset to be xdr=4x in ECP5DDRPHY --- gram/phy/ecp5ddrphy.py | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index d7d68b4..e1d1147 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -235,6 +235,14 @@ class ECP5DDRPHY(Peripheral, Elaboratable): self.pads.clk.o3[i].eq(1), ] + # Reset signal ------------------------ + + rst = Signal(reset_less=True) + drs = ResetSignal("dramsync") + m.d.comb += rst.eq(drs) + #if hasattr(self.pads, "rst"): + + # Addresses and Commands --------------------------------------------------------------- m.d.comb += [ self.pads.a.o_clk.eq(ClockSignal("dramsync")), @@ -273,23 +281,14 @@ class ECP5DDRPHY(Peripheral, Elaboratable): # dfi.Interface it is "reset" dfi2pads = {'rst': 'reset', 'cs': 'cs_n'} name = dfi2pads.get(name, name) # remap if exists - if name == "reset": - m.d.comb += [ - pad.o_clk.eq(ClockSignal("sync")), - ] - else: - m.d.comb += [ + m.d.comb += [ pad.o_clk.eq(ClockSignal("dramsync")), pad.o_prst.eq(ResetSignal("dramsync")), pad.o_fclk.eq(ClockSignal("dramsync2x")), ] - if name == "reset": - for i in range(len(pad.o)): - m.d.comb += [ - pad.o[i].eq(getattr(dfi.phases[0], name)[i]), - ] - elif name == "cs_n": - # cs_n can't be directly connected to cs without being inverted first... + if name == "cs_n": + # cs_n can't be directly connected to cs without + # being inverted first... for i in range(len(pad.o0)): m.d.comb += [ pad.o0[i].eq(~getattr(dfi.phases[0], name)[i]), -- 2.30.2