From ab32fa4ed89213e96028f793a40b43d82e51a3b9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Mar 2022 12:36:06 +0100 Subject: [PATCH] minor simplification of hyperram: using constants in m.If(test) can be done as plain python "if(test)" --- lambdasoc/periph/hyperram.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index 3527ee4..b8bff73 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -242,8 +242,10 @@ class HyperRAM(Peripheral, Elaboratable): # Sequencer ------------------------------------------------------- cycles = Signal(8) first = Signal() + nfirst = Signal() # not-first count_inc = Signal() dbg_cyc = Signal(8) + comb += nfirst.eq(~first) # convenience # when not idle run a cycles counter with m.If(count_inc): @@ -300,7 +302,7 @@ class HyperRAM(Peripheral, Elaboratable): sync += cycles.eq(0) # On last state, see if we can continue the burst # or if we should end it. - with m.If(n == (states - 1)): + if n == states - 1: sync += first.eq(0) # Continue burst when consecutive access ready. with m.If(bus.stb & bus.cyc & @@ -310,12 +312,12 @@ class HyperRAM(Peripheral, Elaboratable): # Early Write Ack (to allow bursting). comb += bus.ack.eq(bus.we) # Else end the burst. - with m.Elif(bus_we | ~first): + with m.Elif(bus_we | nfirst): m.next = "IDLE" sync += cycles.eq(0) # Read Ack (when dat_r ready). - with m.If((n == 0) & ~first): - comb += bus.ack.eq(~bus_we) + if n == 0: + comb += bus.ack.eq(nfirst & ~bus_we) return m -- 2.30.2