From af6b388904fa68e1868b359b335b84f6aa42af8f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 06:53:09 +0100 Subject: [PATCH] clock resolution --- src/bsv/bsv_lib/soc_template.bsv | 1 + src/bsv/peripheral_gen/base.py | 3 ++- src/bsv/peripheral_gen/rgbttl.py | 6 +++--- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 01a05d3..da213b7 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -40,6 +40,7 @@ package socgen; import Clocks::*; /*=== Project imports === */ + import ifc_sync:: *; import ConcatReg::*; import AXI4_Types::*; import AXI4_Fabric::*; diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 92c41d6..7b8ca98 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -235,7 +235,8 @@ else""" if ctype == 'slow': spc = "sp_clock, sp_reset" else: - spc = "fast_clock, fast_reset" + spc = ck + ck = "core_clock, core_reset" template = """\ Ifc_sync#({0}) {1}_sync <-mksyncconnection( {2}, {3});""" diff --git a/src/bsv/peripheral_gen/rgbttl.py b/src/bsv/peripheral_gen/rgbttl.py index ad1027e..91f2eb9 100644 --- a/src/bsv/peripheral_gen/rgbttl.py +++ b/src/bsv/peripheral_gen/rgbttl.py @@ -35,8 +35,7 @@ class rgbttl(PBase): else: sname = self.peripheral.iname().format(count) ps = "pinmux.peripheral_side.%s" % sname - name = self.get_iname(count) - n = "{0}".format(name) + n = self.get_iname(count) for ptype in ['data_out']: ps_ = "{0}.{1}".format(ps, ptype) ret += self._mk_actual_connection('out', name, count, 'out', @@ -51,7 +50,8 @@ class rgbttl(PBase): if ctype == 'slow': spc = "sp_clock, sp_reset" else: - spc = "fast_clock, fast_reset" + spc = ck + ck = "core_clock, core_reset" template = """\ Ifc_sync#({0}) {1}_sync <-mksyncconnection( {2}, {3});""" -- 2.30.2