From b67f1fdb9ff2561060fce855083c8ceae43be071 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Tue, 22 Feb 2022 19:05:13 -0600 Subject: [PATCH] Add Tercel support to Arty NOTE: Untested due to lack of hardware and lack of access to proprietary Xilinx toolchains --- fpga/top-arty.vhdl | 105 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 96 insertions(+), 9 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 4125506..0a46af3 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -25,6 +25,7 @@ entity toplevel is SPI_FLASH_DEF_QUAD : boolean := true; LOG_LENGTH : natural := 512; USE_LITEETH : boolean := false; + USE_TERCEL : boolean := false; UART_IS_16550 : boolean := false; HAS_UART1 : boolean := true ); @@ -110,6 +111,7 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_eth : std_ulogic; + signal wb_ext_is_tercel : std_ulogic; -- DRAM main data wishbone connection signal wb_dram_in : wishbone_master_out; @@ -140,6 +142,10 @@ architecture behaviour of toplevel is signal spi_sdat_oe : std_ulogic_vector(3 downto 0); signal spi_sdat_i : std_ulogic_vector(3 downto 0); + -- SPI main data wishbone connection + signal wb_spiflash_in : wb_io_master_out; + signal wb_spiflash_out : wb_io_slave_out; + -- Fixup various memory sizes based on generics function get_bram_size return natural is begin @@ -199,13 +205,6 @@ begin uart1_txd => uart_pmod_tx, uart1_rxd => uart_pmod_rx, - -- SPI signals - spi_flash_sck => spi_sck, - spi_flash_cs_n => spi_cs_n, - spi_flash_sdat_o => spi_sdat_o, - spi_flash_sdat_oe => spi_sdat_oe, - spi_flash_sdat_i => spi_sdat_i, - -- External interrupts ext_irq_eth => ext_irq_eth, @@ -217,7 +216,12 @@ begin wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_init => wb_ext_is_dram_init, wb_ext_is_eth => wb_ext_is_eth, - alt_reset => core_alt_reset + wb_ext_is_tercel => wb_ext_is_tercel, + alt_reset => core_alt_reset, + + -- SPI wishbone + wb_spiflash_in => wb_spiflash_in, + wb_spiflash_out => wb_spiflash_out ); uart_pmod_rts_n <= '0'; @@ -524,8 +528,91 @@ begin ext_irq_eth <= '0'; end generate; + has_tercel : if USE_TERCEL generate + + component tercel_core port ( + sys_clk_freq : in std_ulogic_vector(31 downto 0); + + peripheral_clock : in std_ulogic; + peripheral_reset : in std_ulogic; + + spi_clock : out std_ulogic; + spi_d_out : out std_ulogic_vector(3 downto 0); + spi_d_direction : out std_ulogic_vector(3 downto 0); + spi_d_in : in std_ulogic_vector(3 downto 0); + spi_ss_n : out std_ulogic; + + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_err : out std_ulogic; + + cfg_wishbone_adr : in std_ulogic_vector(29 downto 0); + cfg_wishbone_dat_w : in std_ulogic_vector(31 downto 0); + cfg_wishbone_dat_r : out std_ulogic_vector(31 downto 0); + cfg_wishbone_sel : in std_ulogic_vector(3 downto 0); + cfg_wishbone_cyc : in std_ulogic; + cfg_wishbone_stb : in std_ulogic; + cfg_wishbone_ack : out std_ulogic; + cfg_wishbone_we : in std_ulogic; + cfg_wishbone_err : out std_ulogic + ); + end component; + + signal wb_tercel_cyc : std_ulogic; + + begin + tercel : tercel_core + port map( + sys_clk_freq => std_logic_vector(to_unsigned(CLK_FREQUENCY, 32)), + + peripheral_clock => system_clk, + peripheral_reset => soc_rst, + + spi_clock => spi_sck, + spi_d_out => spi_sdat_o, + spi_d_direction => spi_sdat_oe, + spi_d_in => spi_sdat_i, + spi_ss_n => spi_cs_n, + + wishbone_adr => wb_spiflash_in.adr, + wishbone_dat_w => wb_spiflash_in.dat, + wishbone_dat_r => wb_spiflash_out.dat, + wishbone_sel => wb_spiflash_in.sel, + wishbone_cyc => wb_spiflash_in.cyc, + wishbone_stb => wb_spiflash_in.stb, + wishbone_ack => wb_spiflash_out.ack, + wishbone_we => wb_spiflash_in.we, + wishbone_err => open, + + cfg_wishbone_adr => wb_ext_io_in.adr, + cfg_wishbone_dat_w => wb_ext_io_in.dat, + cfg_wishbone_dat_r => wb_tercel_out.dat, + cfg_wishbone_sel => wb_ext_io_in.sel, + cfg_wishbone_cyc => wb_tercel_cyc, + cfg_wishbone_stb => wb_ext_io_in.stb, + cfg_wishbone_ack => wb_tercel_out.ack, + cfg_wishbone_we => wb_ext_io_in.we, + cfg_wishbone_err => open + ); + + -- Gate cyc with "chip select" from soc + wb_tercel_cyc <= wb_ext_io_in.cyc and wb_ext_is_tercel; + + -- Tercel isn't pipelined + wb_tercel_out.stall <= not wb_tercel_out.ack; + + end generate; + -- Mux WB response on the IO bus - wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out; + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_tercel_out when wb_ext_is_tercel = '1' else + wb_dram_ctrl_out; leds_pwm : process(system_clk) begin -- 2.30.2