From ba7d6761286ec2ea6e47b89de5dc0599bf7a6f34 Mon Sep 17 00:00:00 2001
From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 7 Aug 2022 19:56:34 +0200
Subject: [PATCH] comment out reset signal for iverilog simulation

---
 src/simsoctb.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/simsoctb.v b/src/simsoctb.v
index 64fb39a..da3b2e0 100644
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -90,7 +90,7 @@ module simsoctb;
   //defparam ram_chip.
   
   top simsoctop (
-    .ddr3_0__rst__io(dram_rst),
+     //FIXME .ddr3_0__rst__io(dram_rst),
     .ddr3_0__dq__io(dram_dq),
     .ddr3_0__dqs__p(dram_dqs),
     .ddr3_0__clk__p(dram_ck),
-- 
2.30.2