From c709ad7d10143a32d9b36e4262f92da989035527 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 May 2021 15:04:23 +0100 Subject: [PATCH] remove wb err signal from sram4k --- libresoc/core.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index 35aac19..853191f 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -25,14 +25,17 @@ def make_wb_bus(prefix, obj, simple=False): res['i_%s__%s' % (prefix, i)] = getattr(obj, i) return res -def make_wb_slave(prefix, obj, simple=False): +def make_wb_slave(prefix, obj, simple=False, err=True): res = {} inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel'] if not simple: inpins += ['cti', 'bte'] for i in inpins: res['i_%s__%s' % (prefix, i)] = getattr(obj, i) - for o in ['ack', 'err', 'dat_r']: + outpins = ['ack', 'dat_r'] + if err: + outpins.append('err') + for o in outpins: res['o_%s__%s' % (prefix, o)] = getattr(obj, o) return res @@ -289,7 +292,8 @@ class LibreSoC(CPU): if "sram4k" in variant: for i, sram in enumerate(srams): self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, - sram, simple=True)) + sram, simple=True, + err=False)) # and set ibus advanced tags to zero (disable) self.cpu_params['i_ibus__cti'] = 0 -- 2.30.2