From cd44c0fc57e955f263760892203575be70202fc4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 26 Mar 2022 21:20:15 +0000 Subject: [PATCH] sort out hyperram ports down to test class --- lambdasoc/periph/hyperram.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index 446e495..02e3d5f 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -94,6 +94,16 @@ class HyperRAMPads: self.cs_n = Signal() self.dq = Record([("oe", 1), ("o", dw), ("i", dw)]) self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)]) + self.dq.o.name = "dq_o" + self.dq.i.name = "dq_i" + self.dq.oe.name = "dq_oe" + self.rwds.o.name = "rwds_o" + self.rwds.i.name = "rwds_i" + self.rwds.oe.name = "rwds_oe" + + def ports(self): + return [self.ck, self.cs, self.dq.o, self.dq.i, self.dq.oe, + self.rwds.o, self.rwds.oe] class HyperRAMPHY(Elaboratable): @@ -114,8 +124,8 @@ class HyperRAMPHY(Elaboratable): return m def ports(self): - return [self.ck, self.cs, self.dq_o, self.dq_i, self.dq_oe, - self.rwds_o, self.rwds_oe] + return self.pads.ports() + # HyperRAM -------------------------------------------------------------------- -- 2.30.2