From d38431065bcb6d98c6a7bad341ae640b968582a1 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 3 Apr 2021 16:04:49 -0300 Subject: [PATCH] Add a test case for integer single predication --- src/soc/fu/alu/test/svp64_cases.py | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index b358c2e5..00a7d0f0 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -339,3 +339,39 @@ class SVP64ALUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) + + # checks integer predication. + def case_13_sv_predicated_add(self): + # adds: + # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + # 2 = 0 (skipped) + # 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230 + # + # 13 = 0 (skipped) + # 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051 + # 15 = 0 (skipped) + isa = SVP64Asm([ + 'sv.add/m=r30 1.v, 5.v, 9.v', + 'sv.add/m=~r30 13.v, 10.v, 7.v' + ]) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[30] = 0b101 # predicate mask + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[11] = 0x3012 + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + initial_regs[7] = 0x1230 + initial_regs[8] = 0x8051 + # SVSTATE (in this case, VL=3) + svstate = SVP64State() + svstate.vl[0:7] = 3 # VL + svstate.maxvl[0:7] = 3 # MAXVL + print("SVSTATE", bin(svstate.spr.asint())) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate) -- 2.30.2