From db1d38524e0a9216138c8fa6ce0dc28d7596d077 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Apr 2019 12:02:58 +0100 Subject: [PATCH] use SimpleHandshake instead of UnbufferedPipeline --- src/add/fpadd/addstages.py | 6 +++--- src/add/fpadd/pipeline.py | 2 +- src/add/fpadd/specialcases.py | 6 +++--- src/add/fpadd/statemachine.py | 2 +- src/add/fpcommon/getop.py | 2 +- src/add/fpcommon/normtopack.py | 6 +++--- src/add/test_inout_mux_pipe.py | 6 +++--- src/add/test_outmux_pipe.py | 6 +++--- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/add/fpadd/addstages.py b/src/add/fpadd/addstages.py index 626a0c0d..f5703aec 100644 --- a/src/add/fpadd/addstages.py +++ b/src/add/fpadd/addstages.py @@ -5,7 +5,7 @@ from nmigen import Module from nmigen.cli import main, verilog -from singlepipe import (StageChain, UnbufferedPipeline, +from singlepipe import (StageChain, SimpleHandshake, PassThroughStage) from fpbase import FPState @@ -16,13 +16,13 @@ from fpadd.add0 import FPAddStage0Mod from fpadd.add1 import FPAddStage1Mod -class FPAddAlignSingleAdd(FPState, UnbufferedPipeline): +class FPAddAlignSingleAdd(FPState, SimpleHandshake): def __init__(self, width, id_wid): FPState.__init__(self, "align") self.width = width self.id_wid = id_wid - UnbufferedPipeline.__init__(self, self) # pipeline is its own stage + SimpleHandshake.__init__(self, self) # pipeline is its own stage self.a1o = self.ospec() def ispec(self): diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py index 45b943ea..6917b678 100644 --- a/src/add/fpadd/pipeline.py +++ b/src/add/fpadd/pipeline.py @@ -5,7 +5,7 @@ from nmigen import Module from nmigen.cli import main, verilog -from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage) +from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage) from multipipe import CombMuxOutPipe from multipipe import PriorityCombMuxInPipe diff --git a/src/add/fpadd/specialcases.py b/src/add/fpadd/specialcases.py index 5c5c7bcd..6f9d1a08 100644 --- a/src/add/fpadd/specialcases.py +++ b/src/add/fpadd/specialcases.py @@ -7,7 +7,7 @@ from nmigen.cli import main, verilog from math import log from fpbase import FPNumDecode -from singlepipe import UnbufferedPipeline, StageChain +from singlepipe import SimpleHandshake, StageChain from fpbase import FPState, FPID from fpcommon.getop import FPADDBaseData @@ -176,7 +176,7 @@ class FPAddSpecialCases(FPState): m.next = "denormalise" -class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline): +class FPAddSpecialCasesDeNorm(FPState, SimpleHandshake): """ special cases: NaNs, infs, zeros, denormalised NOTE: some of these are unique to add. see "Special Operations" https://steve.hollasch.net/cgindex/coding/ieeefloat.html @@ -186,7 +186,7 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline): FPState.__init__(self, "special_cases") self.width = width self.id_wid = id_wid - UnbufferedPipeline.__init__(self, self) # pipe is its own stage + SimpleHandshake.__init__(self, self) # pipe is its own stage self.out = self.ospec() def ispec(self): diff --git a/src/add/fpadd/statemachine.py b/src/add/fpadd/statemachine.py index 9e13205f..1e45cedd 100644 --- a/src/add/fpadd/statemachine.py +++ b/src/add/fpadd/statemachine.py @@ -8,7 +8,7 @@ from math import log from fpbase import FPOp from fpbase import Trigger -from singlepipe import (StageChain, UnbufferedPipeline) +from singlepipe import (StageChain, SimpleHandshake) from fpbase import FPState, FPID from fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op) diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py index 60738431..8cf5e421 100644 --- a/src/add/fpcommon/getop.py +++ b/src/add/fpcommon/getop.py @@ -9,7 +9,7 @@ from math import log from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase from fpbase import MultiShiftRMerge, Trigger -from singlepipe import (ControlBase, StageChain, UnbufferedPipeline, +from singlepipe import (ControlBase, StageChain, SimpleHandshake, PassThroughStage) from multipipe import CombMuxOutPipe from multipipe import PriorityCombMuxInPipe diff --git a/src/add/fpcommon/normtopack.py b/src/add/fpcommon/normtopack.py index 235d8807..14814669 100644 --- a/src/add/fpcommon/normtopack.py +++ b/src/add/fpcommon/normtopack.py @@ -4,7 +4,7 @@ #from nmigen.cli import main, verilog -from singlepipe import StageChain, UnbufferedPipeline +from singlepipe import StageChain, SimpleHandshake from fpbase import FPState, FPID from fpcommon.postcalc import FPAddStage1Data @@ -14,13 +14,13 @@ from fpcommon.corrections import FPCorrectionsMod from fpcommon.pack import FPPackData, FPPackMod -class FPNormToPack(FPState, UnbufferedPipeline): +class FPNormToPack(FPState, SimpleHandshake): def __init__(self, width, id_wid): FPState.__init__(self, "normalise_1") self.id_wid = id_wid self.width = width - UnbufferedPipeline.__init__(self, self) # pipeline is its own stage + SimpleHandshake.__init__(self, self) # pipeline is its own stage def ispec(self): return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py index d0ff6489..92b6f53f 100644 --- a/src/add/test_inout_mux_pipe.py +++ b/src/add/test_inout_mux_pipe.py @@ -13,7 +13,7 @@ from nmigen.cli import verilog, rtlil from multipipe import CombMultiOutPipeline, CombMuxOutPipe from multipipe import PriorityCombMuxInPipe -from singlepipe import UnbufferedPipeline +from singlepipe import SimpleHandshake class PassData: # (Value): @@ -50,9 +50,9 @@ class PassThroughStage: -class PassThroughPipe(UnbufferedPipeline): +class PassThroughPipe(SimpleHandshake): def __init__(self): - UnbufferedPipeline.__init__(self, PassThroughStage()) + SimpleHandshake.__init__(self, PassThroughStage()) class InputTest: diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py index 67b03132..7c25f384 100644 --- a/src/add/test_outmux_pipe.py +++ b/src/add/test_outmux_pipe.py @@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from multipipe import CombMuxOutPipe -from singlepipe import UnbufferedPipeline +from singlepipe import SimpleHandshake class PassInData: @@ -43,9 +43,9 @@ class PassThroughDataStage: -class PassThroughPipe(UnbufferedPipeline): +class PassThroughPipe(SimpleHandshake): def __init__(self): - UnbufferedPipeline.__init__(self, PassThroughDataStage()) + SimpleHandshake.__init__(self, PassThroughDataStage()) -- 2.30.2