From e0a763e534ccbe8689c62906f59f5f9ebfbc27ed Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 31 Jul 2020 08:58:30 +0200 Subject: [PATCH] cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. --- litex/soc/cores/cpu/vexriscv/system.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h index 0683b5b7..f441a197 100644 --- a/litex/soc/cores/cpu/vexriscv/system.h +++ b/litex/soc/cores/cpu/vexriscv/system.h @@ -3,12 +3,17 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif __attribute__((unused)) static void flush_cpu_icache(void) { +#if defined(CONFIG_CPU_VARIANT_MIN) + /* No instruction cache */ +#else asm volatile( ".word(0x100F)\n" "nop\n" @@ -17,19 +22,22 @@ __attribute__((unused)) static void flush_cpu_icache(void) "nop\n" "nop\n" ); +#endif } __attribute__((unused)) static void flush_cpu_dcache(void) { +#if defined(CONFIG_CPU_VARIANT_MIN) || defined(CONFIG_CPU_VARIANT_LITE) + /* No data cache */ +#else asm volatile(".word(0x500F)\n"); +#endif } void flush_l2_cache(void); void busy_wait(unsigned int ms); -#include - #define csrr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -- 2.30.2