From e4ffa78b6ca6cc9ed8d0407c4a73394991003663 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 22 May 2021 12:27:17 +0100 Subject: [PATCH] rename vco_test_ana to pll_testout_o --- libresoc/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libresoc/core.py b/libresoc/core.py index 681ccf6..478bcaf 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -275,7 +275,7 @@ class LibreSoC(CPU): self.pll_ana_o = Signal() self.cpu_params['i_clk_sel_i'] = self.clk_sel self.cpu_params['o_pll_18_o'] = self.pll_18_o - self.cpu_params['o_vco_test_ana'] = self.pll_ana_o + self.cpu_params['o_pll_testout_o'] = self.pll_ana_o # add wishbone buses to cpu params self.cpu_params.update(make_wb_bus("ibus", ibus, True)) -- 2.30.2