From ed10215105361310ef5bccdac1a0c05bccc252e2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 May 2019 07:41:37 +0100 Subject: [PATCH] add test on fp16/32/64 for mul and div --- src/ieee754/fpadd/test/test_fpadd_pipe.py | 135 +++------------------- src/ieee754/fpmul/test/test_fpmul_pipe.py | 9 +- 2 files changed, 25 insertions(+), 119 deletions(-) diff --git a/src/ieee754/fpadd/test/test_fpadd_pipe.py b/src/ieee754/fpadd/test/test_fpadd_pipe.py index 2b021924..9bf0da7d 100644 --- a/src/ieee754/fpadd/test/test_fpadd_pipe.py +++ b/src/ieee754/fpadd/test/test_fpadd_pipe.py @@ -1,127 +1,26 @@ -""" key strategic example showing how to do multi-input fan-in into a - multi-stage pipeline, then multi-output fanout. - - the multiplex ID from the fan-in is passed in to the pipeline, preserved, - and used as a routing ID on the fanout. +""" test of FPADDMuxInOut """ -from random import randint -from math import log -from nmigen import Module, Signal, Cat, Value -from nmigen.compat.sim import run_simulation -from nmigen.cli import verilog, rtlil - -from ieee754.fpadd.nmigen_add_experiment import (FPADDMuxInOut,) - -from sfpy import Float32 - -class InputTest: - def __init__(self, dut): - self.dut = dut - self.di = {} - self.do = {} - self.tlen = 10 - self.width = 32 - for mid in range(dut.num_rows): - self.di[mid] = {} - self.do[mid] = [] - for i in range(self.tlen): - op1 = randint(0, (1<