From ed3310f4ecb907146bf0372ed992f5ae40b17194 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 25 Jul 2018 11:31:49 +0100 Subject: [PATCH] add jtag interface decl --- src/bsv/bsv_lib/soc_template.bsv | 24 ------------------------ src/bsv/peripheral_gen/base.py | 14 ++++++++++++++ src/bsv/peripheral_gen/jtag.py | 18 ++++++++++++++++++ src/bsv/pinmux_generator.py | 3 ++- 4 files changed, 34 insertions(+), 25 deletions(-) diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 94ceec0..a36243b 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -82,30 +82,6 @@ package Soc; `ifdef DDR (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master; `endif - `ifdef Debug - (*always_ready,always_enabled*) - method Action tms_i(Bit#(1) tms); - (*always_ready,always_enabled*) - method Action tdi_i(Bit#(1) tdi); - (*always_ready,always_enabled*) - method Action bs_chain_i(Bit#(1) bs_chain); - (*always_ready,always_enabled*) - method Bit#(1) shiftBscan2Edge; - (*always_ready,always_enabled*) - method Bit#(1) selectJtagInput; - (*always_ready,always_enabled*) - method Bit#(1) selectJtagOutput; - (*always_ready,always_enabled*) - method Bit#(1) updateBscan; - (*always_ready,always_enabled*) - method Bit#(1) bscan_in; - (*always_ready,always_enabled*) - method Bit#(1) scan_shift_en; - (*always_ready,always_enabled*) - method Bit#(1) tdo; - (*always_ready,always_enabled*) - method Bit#(1) tdo_oe; - `endif `ifdef HYPER (*always_ready,always_enabled*) interface Ifc_flash ifc_flash; diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 6d680f6..51c87e8 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -12,6 +12,9 @@ class PBase(object): def has_axi_master(self): return False + def fastifdecl(self, name, count): + return '' + def slowifdeclmux(self, name, count): return '' @@ -286,6 +289,7 @@ class PeripheralIface(object): for fname in ['slowimport', 'extifinstance', 'extifdecl', 'slowifdecl', 'slowifdeclmux', + 'fastifdecl', 'mkslow_peripheral', 'mkfast_peripheral', 'mk_plic', 'mk_ext_ifacedef', @@ -359,6 +363,16 @@ class PeripheralInterfaces(object): ret.append(self.data[name].slowifdeclmux(name, i)) return '\n'.join(list(filter(None, ret))) + def fastifdecl(self, *args): + ret = [] + for (name, count) in self.ifacecount: + for i in range(count): + print "fastifdecl", name, i, self.is_on_fastbus(name, i) + if self.is_on_fastbus(name, i): + continue + ret.append(self.data[name].fastifdecl(name, i)) + return '\n'.join(list(filter(None, ret))) + def slowifdecl(self, *args): ret = [] for (name, count) in self.ifacecount: diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py index 45025c6..7510609 100644 --- a/src/bsv/peripheral_gen/jtag.py +++ b/src/bsv/peripheral_gen/jtag.py @@ -6,6 +6,24 @@ class jtag(PBase): def slowimport(self): return " import jtagtdm::*;\n" + def fastifdecl(self, name, count): + # YUK! + template = """ \ + (*always_ready,always_enabled*) method Action tms_i(Bit#(1) tms); + (*always_ready,always_enabled*) method Action tdi_i(Bit#(1) tdi); + (*always_ready,always_enabled*) + method Action bs_chain_i(Bit#(1) bs_chain); + (*always_ready,always_enabled*) method Bit#(1) shiftBscan2Edge; + (*always_ready,always_enabled*) method Bit#(1) selectJtagInput; + (*always_ready,always_enabled*) method Bit#(1) selectJtagOutput; + (*always_ready,always_enabled*) method Bit#(1) updateBscan; + (*always_ready,always_enabled*) method Bit#(1) bscan_in; + (*always_ready,always_enabled*) method Bit#(1) scan_shift_en; + (*always_ready,always_enabled*) method Bit#(1) tdo; + (*always_ready,always_enabled*) method Bit#(1) tdo_oe; +""" + return template + def mkfast_peripheral(self): return """\ Ifc_jtagdtm jtag{0} <-mkjtagdtm(clocked_by tck, reset_by trst); diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 485e180..31b5c4d 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -132,7 +132,8 @@ def write_soc(soc, soct, p, ifaces, iocells): with open(soct) as bsv_file: soct = bsv_file.read() imports = ifaces.slowimport() - ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() + ifdecl = ifaces.fastifdecl() +#ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() regdef = ifaces.axi_reg_def() slavedecl = ifaces.axi_fastslave_idx() mastdecl = ifaces.axi_master_idx() -- 2.30.2