From f21fcb8e15c6a1a402599717936a37a2cd80ab2e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 Mar 2019 20:15:16 +0000 Subject: [PATCH] add test, temporary comb variable to stage2 --- src/add/pipeline_example.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/add/pipeline_example.py b/src/add/pipeline_example.py index 544b745b..590e1db6 100644 --- a/src/add/pipeline_example.py +++ b/src/add/pipeline_example.py @@ -22,7 +22,9 @@ class SimplePipelineExample(SimplePipeline): self.n = self.n + 1 def stage2(self): - self.n = self.n << 1 + localv = Signal(4) + self._pipe.comb += localv.eq(2) + self.n = self.n << localv def stage3(self): self.n = ~self.n @@ -45,6 +47,6 @@ if __name__ == "__main__": example.p._loopback, ]) - print(verilog.convert(example, ports=[ - example.p._loopback, - ])) + #print(verilog.convert(example, ports=[ + # example.p._loopback, + # ])) -- 2.30.2