From f44852519032d3db7503cb703a840a1344fbf4cf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 Mar 2019 21:42:53 +0000 Subject: [PATCH] add sync pipe to outmux test --- src/add/test_outmux_pipe.py | 50 ++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py index 325afae4..560ef738 100644 --- a/src/add/test_outmux_pipe.py +++ b/src/add/test_outmux_pipe.py @@ -5,6 +5,7 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from multipipe import CombMultiOutPipeline +from singlepipe import UnbufferedPipeline class MuxUnbufferedPipeline(CombMultiOutPipeline): @@ -43,6 +44,23 @@ class PassThroughStage: return i.data +class PassThroughDataStage: + def ispec(self): + return PassInData() + def ospec(self): + return self.ispec() # same as ospec + + def process(self, i): + return i # pass-through + + + +class PassThroughPipe(UnbufferedPipeline): + def __init__(self): + UnbufferedPipeline.__init__(self, PassThroughDataStage()) + + + def testbench(dut): stb = yield dut.out_op.stb @@ -210,8 +228,8 @@ class OutputTest: class TestPriorityMuxPipe(MuxUnbufferedPipeline): - def __init__(self): - self.num_rows = 4 + def __init__(self, num_rows): + self.num_rows = num_rows stage = PassThroughStage() MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows) @@ -225,8 +243,34 @@ class TestPriorityMuxPipe(MuxUnbufferedPipeline): return res +class TestSyncToPriorityPipe: + def __init__(self): + self.num_rows = 4 + self.pipe = PassThroughPipe() + self.muxpipe = TestPriorityMuxPipe(self.num_rows) + + self.p = self.pipe.p + self.n = self.muxpipe.n + + def elaborate(self, platform): + m = Module() + m.submodules += self.pipe + m.submodules += self.muxpipe + m.d.comb += self.pipe.n.connect_to_next(self.muxpipe.p) + return m + + def ports(self): + res = [self.p.i_valid, self.p.o_ready] + \ + self.p.i_data.ports() + for i in range(len(self.n)): + res += [self.n[i].i_ready, self.n[i].o_valid] + \ + [self.n[i].o_data] + #self.n[i].o_data.ports() + return res + + if __name__ == '__main__': - dut = TestPriorityMuxPipe() + dut = TestSyncToPriorityPipe() vl = rtlil.convert(dut, ports=dut.ports()) with open("test_outmux_pipe.il", "w") as f: f.write(vl) -- 2.30.2