From f6905d80347b2c6b5fe2e7a5c8c34614c7562af7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 30 Apr 2022 14:25:37 +0100
Subject: [PATCH] update arty a7 clock frequency to 27 mhz, works with QSPI and
 is within timing

---
 src/ls2.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ls2.py b/src/ls2.py
index 89d6c06..157c1eb 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -868,7 +868,7 @@ def build_platform(fpga, firmware):
         clk_freq = 50e6
         dram_clk_freq = 100e6
     if fpga == 'arty_a7':
-        clk_freq = 50e6
+        clk_freq = 27e6 # urrr "working" with the QSPI core (25 mhz does not)
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
-- 
2.30.2