From fa09d8179f00a731f6a39d039d97188b0ec758d6 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 12 Oct 2017 12:05:26 -0700 Subject: [PATCH] Update to latest debug_defines.h. --- riscv/debug_defines.h | 841 ++++++++++++++++++++---------------------- riscv/debug_module.cc | 26 +- riscv/debug_module.h | 9 +- 3 files changed, 411 insertions(+), 465 deletions(-) diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h index cb07ec2..6067dbe 100644 --- a/riscv/debug_defines.h +++ b/riscv/debug_defines.h @@ -4,13 +4,13 @@ */ #define DTM_IDCODE_VERSION_OFFSET 28 #define DTM_IDCODE_VERSION_LENGTH 4 -#define DTM_IDCODE_VERSION (0xf << DTM_IDCODE_VERSION_OFFSET) +#define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET) /* * Identifies the designer's part number of this part. */ #define DTM_IDCODE_PARTNUMBER_OFFSET 12 #define DTM_IDCODE_PARTNUMBER_LENGTH 16 -#define DTM_IDCODE_PARTNUMBER (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET) +#define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET) /* * Identifies the designer/manufacturer of this part. Bits 6:0 must be * bits 6:0 of the designer/manufacturer's Identification Code as @@ -20,10 +20,10 @@ */ #define DTM_IDCODE_MANUFID_OFFSET 1 #define DTM_IDCODE_MANUFID_LENGTH 11 -#define DTM_IDCODE_MANUFID (0x7ff << DTM_IDCODE_MANUFID_OFFSET) +#define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET) #define DTM_IDCODE_1_OFFSET 0 #define DTM_IDCODE_1_LENGTH 1 -#define DTM_IDCODE_1 (0x1 << DTM_IDCODE_1_OFFSET) +#define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET) #define DTM_DTMCS 0x10 /* * Writing 1 to this bit does a hard reset of the DTM, @@ -35,7 +35,7 @@ */ #define DTM_DTMCS_DMIHARDRESET_OFFSET 17 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 -#define DTM_DTMCS_DMIHARDRESET (0x1 << DTM_DTMCS_DMIHARDRESET_OFFSET) +#define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET) /* * Writing 1 to this bit clears the sticky error state * and allows the DTM to retry or complete the previous @@ -43,7 +43,7 @@ */ #define DTM_DTMCS_DMIRESET_OFFSET 16 #define DTM_DTMCS_DMIRESET_LENGTH 1 -#define DTM_DTMCS_DMIRESET (0x1 << DTM_DTMCS_DMIRESET_OFFSET) +#define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET) /* * This is a hint to the debugger of the minimum number of * cycles a debugger should spend in @@ -61,7 +61,7 @@ */ #define DTM_DTMCS_IDLE_OFFSET 12 #define DTM_DTMCS_IDLE_LENGTH 3 -#define DTM_DTMCS_IDLE (0x7 << DTM_DTMCS_IDLE_OFFSET) +#define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET) /* * 0: No error. * @@ -74,24 +74,24 @@ */ #define DTM_DTMCS_DMISTAT_OFFSET 10 #define DTM_DTMCS_DMISTAT_LENGTH 2 -#define DTM_DTMCS_DMISTAT (0x3 << DTM_DTMCS_DMISTAT_OFFSET) +#define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET) /* * The size of \Faddress in \Rdmi. */ #define DTM_DTMCS_ABITS_OFFSET 4 #define DTM_DTMCS_ABITS_LENGTH 6 -#define DTM_DTMCS_ABITS (0x3f << DTM_DTMCS_ABITS_OFFSET) +#define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET) /* * 0: Version described in spec version 0.11. * -* 1: Version described in spec version 0.12 (and later?), which +* 1: Version described in spec version 0.13 (and later?), which * reduces the DMI data width to 32 bits. * -* Other values are reserved for future use. +* 15: Version not described in any available version of this spec. */ #define DTM_DTMCS_VERSION_OFFSET 0 #define DTM_DTMCS_VERSION_LENGTH 4 -#define DTM_DTMCS_VERSION (0xf << DTM_DTMCS_VERSION_OFFSET) +#define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET) #define DTM_DMI 0x11 /* * Address used for DMI access. In Update-DR this value is used @@ -106,11 +106,16 @@ */ #define DTM_DMI_DATA_OFFSET 2 #define DTM_DMI_DATA_LENGTH 32 -#define DTM_DMI_DATA (0xffffffffL << DTM_DMI_DATA_OFFSET) +#define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET) /* * When the debugger writes this field, it has the following meaning: * -* 0: Ignore \Fdata. (nop) +* 0: Ignore \Fdata and \Faddress. (nop) +* +* Don't send anything over the DMI during Update-DR. +* This operation should never result in a busy or error response. +* The address and data reported in the following Capture-DR +* are undefined. * * 1: Read from \Faddress. (read) * @@ -128,8 +133,10 @@ * this access will be ignored. This status is sticky and can be * cleared by writing \Fdmireset in \Rdtmcs. * -* This indicates that the DM itself responded with an error, e.g. -* in the System Bus and Serial Port overflow/underflow cases. +* This indicates that the DM itself responded with an error. +* Note: there are no specified cases in which the DM would +* respond with an error, and DMI is not required to support +* returning errors. * * 3: An operation was attempted while a DMI request is still in * progress. The data scanned into \Rdmi in this access will be @@ -146,49 +153,58 @@ */ #define DTM_DMI_OP_OFFSET 0 #define DTM_DMI_OP_LENGTH 2 -#define DTM_DMI_OP (0x3L << DTM_DMI_OP_OFFSET) +#define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET) #define CSR_DCSR 0x7b0 /* * 0: There is no external debug support. * -* 1: External debug support exists as it is described in this document. +* 4: External debug support exists as it is described in this document. * -* Other values are reserved for future standards. +* 15: There is external debug support, but it does not conform to any +* available version of this spec. */ -#define CSR_DCSR_XDEBUGVER_OFFSET 30 -#define CSR_DCSR_XDEBUGVER_LENGTH 2 -#define CSR_DCSR_XDEBUGVER (0x3 << CSR_DCSR_XDEBUGVER_OFFSET) +#define CSR_DCSR_XDEBUGVER_OFFSET 28 +#define CSR_DCSR_XDEBUGVER_LENGTH 4 +#define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET) /* * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode. */ #define CSR_DCSR_EBREAKM_OFFSET 15 #define CSR_DCSR_EBREAKM_LENGTH 1 -#define CSR_DCSR_EBREAKM (0x1 << CSR_DCSR_EBREAKM_OFFSET) -/* -* When 1, {\tt ebreak} instructions in Hypervisor Mode enter Debug Mode. - */ -#define CSR_DCSR_EBREAKH_OFFSET 14 -#define CSR_DCSR_EBREAKH_LENGTH 1 -#define CSR_DCSR_EBREAKH (0x1 << CSR_DCSR_EBREAKH_OFFSET) +#define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET) /* * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode. */ #define CSR_DCSR_EBREAKS_OFFSET 13 #define CSR_DCSR_EBREAKS_LENGTH 1 -#define CSR_DCSR_EBREAKS (0x1 << CSR_DCSR_EBREAKS_OFFSET) +#define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET) /* * When 1, {\tt ebreak} instructions in User/Application Mode enter * Debug Mode. */ #define CSR_DCSR_EBREAKU_OFFSET 12 #define CSR_DCSR_EBREAKU_LENGTH 1 -#define CSR_DCSR_EBREAKU (0x1 << CSR_DCSR_EBREAKU_OFFSET) +#define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET) +/* +* 0: Interrupts are disabled during single stepping. +* +* 1: Interrupts are enabled during single stepping. +* +* Implementations may hard wire this bit to 0. +* The debugger must read back the value it +* writes to check whether the feature is supported. If not +* supported, interrupt behavior can be emulated by the debugger. + */ +#define CSR_DCSR_STEPIE_OFFSET 11 +#define CSR_DCSR_STEPIE_LENGTH 1 +#define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET) /* * 0: Increment counters as usual. * -* 1: Don't increment any counters while in Debug Mode. This includes -* the {\tt cycle} and {\tt instret} CSRs. This is preferred for most -* debugging scenarios. +* 1: Don't increment any counters while in Debug Mode or on {\tt +* ebreak} instructions that cause entry into Debug Mode. These +* counters include the {\tt cycle} and {\tt instret} CSRs. This is +* preferred for most debugging scenarios. * * An implementation may choose not to support writing to this bit. * The debugger must read back the value it writes to check whether @@ -196,7 +212,7 @@ */ #define CSR_DCSR_STOPCOUNT_OFFSET 10 #define CSR_DCSR_STOPCOUNT_LENGTH 1 -#define CSR_DCSR_STOPCOUNT (0x1 << CSR_DCSR_STOPCOUNT_OFFSET) +#define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET) /* * 0: Increment timers as usual. * @@ -208,7 +224,7 @@ */ #define CSR_DCSR_STOPTIME_OFFSET 9 #define CSR_DCSR_STOPTIME_LENGTH 1 -#define CSR_DCSR_STOPTIME (0x1 << CSR_DCSR_STOPTIME_OFFSET) +#define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET) /* * Explains why Debug Mode was entered. * @@ -217,9 +233,9 @@ * * 1: An {\tt ebreak} instruction was executed. (priority 3) * -* 2: The Trigger Module caused a halt. (priority 4) +* 2: The Trigger Module caused a breakpoint exception. (priority 4) * -* 3: \Fhaltreq was set. (priority 2) +* 3: The debugger requested entry to Debug Mode. (priority 2) * * 4: The hart single stepped because \Fstep was set. (priority 1) * @@ -227,18 +243,17 @@ */ #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 -#define CSR_DCSR_CAUSE (0x7 << CSR_DCSR_CAUSE_OFFSET) +#define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) /* * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. -* Interrupts are disabled when this bit is set. * If the instruction does not complete due to an exception, * the hart will immediately enter Debug Mode before executing * the trap handler, with appropriate exception registers set. */ #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 -#define CSR_DCSR_STEP (0x1 << CSR_DCSR_STEP_OFFSET) +#define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET) /* * Contains the privilege level the hart was operating in when Debug * Mode was entered. The encoding is described in Table @@ -251,23 +266,13 @@ */ #define CSR_DCSR_PRV_OFFSET 0 #define CSR_DCSR_PRV_LENGTH 2 -#define CSR_DCSR_PRV (0x3 << CSR_DCSR_PRV_OFFSET) +#define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET) #define CSR_DPC 0x7b1 #define CSR_DPC_DPC_OFFSET 0 #define CSR_DPC_DPC_LENGTH XLEN #define CSR_DPC_DPC (((1L<> i) & 1)) { perform_abstract_command(); } - } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) { + } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; result = read32(program_buffer, i); if (abstractcs.busy) { @@ -313,15 +313,15 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy); - result = set_field(result, DMI_DMSTATUS_VERSIONHI, dmstatus.versionhi); - result = set_field(result, DMI_DMSTATUS_VERSIONLO, dmstatus.versionlo); + result = set_field(result, DMI_DMSTATUS_VERSION, dmstatus.version); } break; case DMI_ABSTRACTCS: result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr); result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy); result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount); - result = set_field(result, DMI_ABSTRACTCS_PROGSIZE, abstractcs.progsize); + result = set_field(result, DMI_ABSTRACTCS_PROGBUFSIZE, + abstractcs.progbufsize); break; case DMI_ABSTRACTAUTO: result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf); @@ -440,7 +440,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) } return true; - } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) { + } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) { unsigned i = address - DMI_PROGBUF0; if (!abstractcs.busy) diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 8b209fb..f6f2009 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -31,8 +31,7 @@ typedef struct { bool authenticated; bool authbusy; bool cfgstrvalid; - unsigned versionhi; - unsigned versionlo; + unsigned version; } dmstatus_t; typedef enum cmderr { @@ -47,7 +46,7 @@ typedef enum cmderr { typedef struct { bool busy; unsigned datacount; - unsigned progsize; + unsigned progbufsize; cmderr_t cmderr; } abstractcs_t; @@ -59,7 +58,7 @@ typedef struct { class debug_module_t : public abstract_device_t { public: - debug_module_t(sim_t *sim, unsigned progsize); + debug_module_t(sim_t *sim, unsigned progbufsize); ~debug_module_t(); void add_device(bus_t *bus); @@ -77,7 +76,7 @@ class debug_module_t : public abstract_device_t static const unsigned datasize = 2; // Size of program_buffer in 32-bit words, as exposed to the rest of the // world. - unsigned progsize; + unsigned progbufsize; // Actual size of the program buffer, which is 1 word bigger than we let on // to implement the implicit ebreak at the end. unsigned program_buffer_bytes; -- 2.30.2