From d48d22ca2b5e297e1b727dc5d626521ffc70bef8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 10:05:36 +0100 Subject: [PATCH 01/16] add test and convert jtag to get/put --- src/peripherals/jtagdtm/Makefile | 45 +++++++++++++++++++ src/peripherals/jtagdtm/jtagdtm.bsv | 44 +++++++++++++----- .../jtagdtm/test/instance_defines.bsv | 24 ++++++++++ 3 files changed, 102 insertions(+), 11 deletions(-) create mode 100644 src/peripherals/jtagdtm/Makefile create mode 100644 src/peripherals/jtagdtm/test/instance_defines.bsv diff --git a/src/peripherals/jtagdtm/Makefile b/src/peripherals/jtagdtm/Makefile new file mode 100644 index 0000000..4991d96 --- /dev/null +++ b/src/peripherals/jtagdtm/Makefile @@ -0,0 +1,45 @@ +### Makefile for the cclass project + +TOP_MODULE:=mkjtagdtm +TOP_FILE:=jtagdtm.bsv +TOP_DIR:=./ +WORKING_DIR := $(shell pwd) + +BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/ +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4 +BSVINCDIR:= $(BSVINCDIR):../../lib +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite +BSVINCDIR:= $(BSVINCDIR):./test + +default: gen_verilog + +check-blue: + @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; + +###### Setting the variables for bluespec compile #$############################ +BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules +BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires +VERILOGDIR:=./verilog/ +BSVBUILDDIR:=./bsv_build/ +BSVOUTDIR:=./bin +################################################################################ + +########## BSIM COMPILE, LINK AND SIMULATE TARGETS ########################## +.PHONY: check-restore +check-restore: + @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi; + +.PHONY: gen_verilog +gen_verilog: check-restore check-blue + @echo Compiling mkTbSoc in Verilog for simulations ... + @mkdir -p $(BSVBUILDDIR); + @mkdir -p $(VERILOGDIR); + bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log + @echo Compilation finished + +############################################################################# + +.PHONY: clean +clean: + rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl* + rm -rf verilog obj_dir bsv_src diff --git a/src/peripherals/jtagdtm/jtagdtm.bsv b/src/peripherals/jtagdtm/jtagdtm.bsv index aea5b37..cf5ae69 100644 --- a/src/peripherals/jtagdtm/jtagdtm.bsv +++ b/src/peripherals/jtagdtm/jtagdtm.bsv @@ -15,13 +15,14 @@ package jtagdtm; /*====== Package imports ======= */ import Clocks::*; import ConcatReg::*; + import GetPut::*; import FIFO::*; import FIFOF::*; import SpecialFIFOs::*; import DReg::*; /*======= Project imports ===== */ `include "jtagdefines.bsv" - import defined_types::*; + //import defined_types::*; /*============================== */ interface Ifc_jtagdtm; @@ -69,15 +70,18 @@ interface Ifc_jtagdtm; method Bit#(1) scan_shift_en; /*======== JTAG input pins ===== */ (*always_enabled,always_ready*) - method Action tms_i(Bit#(1) tms); + interface Put#(Bit#(1)) tms; (*always_enabled,always_ready*) - method Action tdi_i(Bit#(1) tdi); + interface Put#(Bit#(1)) tdi; /*==== inputs from Sub-modules === */ method Action debug_tdi_i(Bit#(1) debug_tdi); /*======= JTAG Output Pins ====== */ (*always_enabled,always_ready*) - method Bit#(1) tdo; + interface Get#(Bit#(1)) tdo; method Bit#(1) tdo_oe; + (*always_enabled,always_ready*) + interface Get#(Bit#(1)) tck; + /*======== TAP States ============= */ method Bit#(1) shift_dr; method Bit#(1) pause_dr; @@ -514,12 +518,19 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 scan_out_5_sr<=scan_out_5; endmethod /*======== JTAG input pins ===== */ - method Action tms_i(Bit#(1) tms); - wr_tms<=tms; - endmethod - method Action tdi_i(Bit#(1) tdi); - wr_tdi<=tdi; - endmethod + + interface tms = interface Put + method Action put(Bit#(1) in); + wr_tms<=in; + endmethod + endinterface; + + interface tdi = interface Put + method Action put(Bit#(1) in); + wr_tdi<=in; + endmethod + endinterface; + /*============================= */ method Action debug_tdi_i(Bit#(1) debug_tdi); wr_debug_tdi<=debug_tdi; @@ -552,7 +563,18 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 method bscan_in = bs_sr; method scan_shift_en = wr_scan_shift_en[1]; /*======= JTAG Output Pins ====== */ - method tdo = crossed_output_tdo; + interface tck = interface Get + method ActionValue#(Bit#(1)) get; + return 'b1; //#def_clk; + endmethod + endinterface; + + interface tdo = interface Get + method ActionValue#(Bit#(1)) get; + return crossed_output_tdo; + endmethod + endinterface; + method debug_tdo = wr_tdi; method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0; method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull); diff --git a/src/peripherals/jtagdtm/test/instance_defines.bsv b/src/peripherals/jtagdtm/test/instance_defines.bsv new file mode 100644 index 0000000..38780f5 --- /dev/null +++ b/src/peripherals/jtagdtm/test/instance_defines.bsv @@ -0,0 +1,24 @@ +`define ADDR 32 +`define PADDR 32 +`define DATA 64 +`define Reg_width 64 +`define USERSPACE 0 + +// TODO: work out if these are needed +`define PWM_AXI4Lite +`define PRFDEPTH 6 +`define VADDR 39 +`define DCACHE_BLOCK_SIZE 4 +`define DCACHE_WORD_SIZE 8 +`define PERFMONITORS 64 +`define DCACHE_WAYS 4 +`define DCACHE_TAG_BITS 20 // tag_bits = 52 +`define PLIC + `define PLICBase 'h0c000000 + `define PLICEnd 'h10000000 +`define INTERRUPT_PINS 64 + +`define BAUD_RATE 130 +`ifdef simulate + `define BAUD_RATE 5 //130 // +`endif -- 2.30.2 From 90cb1d56952f77a0d6830f2ddf67640ca51e0d61 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 10:18:32 +0100 Subject: [PATCH 02/16] tdo_oe is actually tms --- src/peripherals/jtagdtm/jtagdtm.bsv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/peripherals/jtagdtm/jtagdtm.bsv b/src/peripherals/jtagdtm/jtagdtm.bsv index cf5ae69..3bb63a3 100644 --- a/src/peripherals/jtagdtm/jtagdtm.bsv +++ b/src/peripherals/jtagdtm/jtagdtm.bsv @@ -78,7 +78,6 @@ interface Ifc_jtagdtm; /*======= JTAG Output Pins ====== */ (*always_enabled,always_ready*) interface Get#(Bit#(1)) tdo; - method Bit#(1) tdo_oe; (*always_enabled,always_ready*) interface Get#(Bit#(1)) tck; @@ -565,7 +564,7 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 /*======= JTAG Output Pins ====== */ interface tck = interface Get method ActionValue#(Bit#(1)) get; - return 'b1; //#def_clk; + return ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0; endmethod endinterface; @@ -576,7 +575,6 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 endinterface; method debug_tdo = wr_tdi; - method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0; method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull); if(capture_repsonse_from_dm) response_from_DM.enq(responsedm); -- 2.30.2 From 9630336b1b983ed25e7c451cf008d45fae389b6d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 11:28:33 +0100 Subject: [PATCH 03/16] add always_ready to flexbus get/puts --- src/peripherals/flexbus/FlexBus_Types.bsv | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/peripherals/flexbus/FlexBus_Types.bsv b/src/peripherals/flexbus/FlexBus_Types.bsv index f46fae5..19ba1a4 100644 --- a/src/peripherals/flexbus/FlexBus_Types.bsv +++ b/src/peripherals/flexbus/FlexBus_Types.bsv @@ -67,19 +67,30 @@ interface FlexBus_Master_IFC; // FlexBus External Signals // AD inout bus separate for now in BSV + (* always_ready *) interface Get#(Bit#(32)) m_AD; // out + (* always_ready *) interface Put#(Bit#(32)) m_din; // in + (* always_ready *) interface Get#(Bit#(32)) m_OE32n; // out 32-bits, same as OEn + (* always_ready *) interface Get#(Bit#(1)) m_R_Wn; // out + (* always_ready *) interface Get#(Bit#(2)) m_TSIZ; // out + (* always_ready *) interface Get#(Bit#(6)) m_FBCSn; // out + (* always_ready *) interface Get#(Bit#(4)) m_BWEn; // out + (* always_ready *) interface Get#(Bit#(1)) m_TBSTn; // out + (* always_ready *) interface Get#(Bit#(1)) m_OEn; // out + (* always_ready *) interface Get#(Bit#(1)) m_ALE; // out + (* always_ready *) interface Put#(Bit#(1)) m_tAn; // in endinterface: FlexBus_Master_IFC -- 2.30.2 From 0128c8f8effb17f73ce277415573165cded44176 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 11:37:02 +0100 Subject: [PATCH 04/16] add always ready/enabled to get/put --- src/lib/ifc_sync.bsv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/ifc_sync.bsv b/src/lib/ifc_sync.bsv index bfdd8c3..c179206 100644 --- a/src/lib/ifc_sync.bsv +++ b/src/lib/ifc_sync.bsv @@ -3,6 +3,7 @@ package ifc_sync; import Clocks::*; import GetPut::*; + (*always_ready,always_enabled*) interface Ifc_sync#(type a); interface Put#(a) put; interface Get#(a) get; -- 2.30.2 From 44fa1ae0b4f557f069ed2f7738c1a4377b114d25 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 11:38:22 +0100 Subject: [PATCH 05/16] add always ready/enabled to get/put --- src/lib/ifc_sync.bsv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/ifc_sync.bsv b/src/lib/ifc_sync.bsv index c179206..49da823 100644 --- a/src/lib/ifc_sync.bsv +++ b/src/lib/ifc_sync.bsv @@ -5,7 +5,9 @@ package ifc_sync; (*always_ready,always_enabled*) interface Ifc_sync#(type a); + (*always_ready,always_enabled*) interface Put#(a) put; + (*always_ready,always_enabled*) interface Get#(a) get; endinterface module mksyncconnection#(Clock putclock, Reset putreset, -- 2.30.2 From df9621ad270f10a2f59262cb5d6c5898fd50bbf4 Mon Sep 17 00:00:00 2001 From: rahulb Date: Mon, 30 Jul 2018 16:28:36 +0530 Subject: [PATCH 06/16] PLIC modified to support interrupts upto 1024 --- src/peripherals/plic/encoder.bsv | 131 +++++++++++++++ src/peripherals/plic/plic.bsv | 273 ++++++++++++++++--------------- 2 files changed, 268 insertions(+), 136 deletions(-) create mode 100644 src/peripherals/plic/encoder.bsv diff --git a/src/peripherals/plic/encoder.bsv b/src/peripherals/plic/encoder.bsv new file mode 100644 index 0000000..4a26491 --- /dev/null +++ b/src/peripherals/plic/encoder.bsv @@ -0,0 +1,131 @@ +package encoder; + +import Vector ::* ; +`define INPUT 1024 +`define OUTPUT 10 +interface Ifc_encoder#(numeric type irpins); + method Bit#(TLog#(irpins)) encode(Bit#(irpins) ip); +endinterface + +module mkencoder(Ifc_encoder#(irpins)) + provisos(Log#(irpins, irid), + Add#(a__, irpins, `INPUT), + Add#(b__, irid, `OUTPUT)); + function Bit#(irid) fn_encoder(Bit#(irpins) irp); + Bit#(`INPUT) ip = zeroExtend(irp); + Bit#(`OUTPUT) result=0; + Vector#(TDiv#(`INPUT,2),Bit#(1)) ip1; + Vector#(TDiv#(`INPUT,4),Bit#(1)) ip2; + Vector#(TDiv#(`INPUT,8),Bit#(1)) ip3; + Vector#(TDiv#(`INPUT,16),Bit#(1)) ip4; + Vector#(TDiv#(`INPUT,32),Bit#(1)) ip5; + Vector#(TDiv#(`INPUT,64),Bit#(1)) ip6; + Vector#(TDiv#(`INPUT,128),Bit#(1)) ip7; + Vector#(TDiv#(`INPUT,256),Bit#(1)) ip8; + Vector#(TDiv#(`INPUT,512),Bit#(1)) ip9; + Vector#(TDiv#(`INPUT,2),Bit#(1)) pp1; + Vector#(TDiv#(`INPUT,4),Bit#(1)) pp2; + Vector#(TDiv#(`INPUT,8),Bit#(1)) pp3; + Vector#(TDiv#(`INPUT,16),Bit#(1)) pp4; + Vector#(TDiv#(`INPUT,32),Bit#(1)) pp5; + Vector#(TDiv#(`INPUT,64),Bit#(1)) pp6; + Vector#(TDiv#(`INPUT,128),Bit#(1)) pp7; + Vector#(TDiv#(`INPUT,256),Bit#(1)) pp8; + Vector#(TDiv#(`INPUT,512),Bit#(1)) pp9; + Bit#(1) ip10; + Bit#(1) pp10; + + for(Integer i=0;i<`INPUT/2;i=i+1) begin + ip1[i]=ip[i*2+1] | ip[i*2]; + end + for(Integer i=0;i<`INPUT/4;i=i+1) begin + ip2[i]=ip1[i*2+1] | ip1[i*2]; + end + for(Integer i=0;i<`INPUT/8;i=i+1) begin + ip3[i]=ip2[i*2+1] | ip2[i*2]; + end + for(Integer i=0;i<`INPUT/16;i=i+1) begin + ip4[i]=ip3[i*2+1] | ip3[i*2]; + end + for(Integer i=0;i<`INPUT/32;i=i+1) begin + ip5[i]=ip4[i*2+1] | ip4[i*2]; + end + for(Integer i=0;i<`INPUT/64;i=i+1) begin + ip6[i]=ip5[i*2+1] | ip5[i*2]; + end + for(Integer i=0;i<`INPUT/128;i=i+1) begin + ip7[i]=ip6[i*2+1] | ip6[i*2]; + end + for(Integer i=0;i<`INPUT/256;i=i+1) begin + ip8[i]=ip7[i*2+1] | ip7[i*2]; + end + for(Integer i=0;i<`INPUT/512;i=i+1) begin + ip9[i]=ip8[i*2+1] | ip8[i*2]; + end + + for(Integer i=0;i<`INPUT/2;i=i+1) begin + pp1[i]=ip[i*2+1]==1?1:ip[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/4;i=i+1) begin + pp2[i]=ip1[i*2+1]==1?1:ip1[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/8;i=i+1) begin + pp3[i]=ip2[i*2+1]==1?1:ip2[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/16;i=i+1) begin + pp4[i]=ip3[i*2+1]==1?1:ip3[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/32;i=i+1) begin + pp5[i]=ip4[i*2+1]==1?1:ip4[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/64;i=i+1) begin + pp6[i]=ip5[i*2+1]==1?1:ip5[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/128;i=i+1) begin + pp7[i]=ip6[i*2+1]==1?1:ip6[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/256;i=i+1) begin + pp8[i]=ip7[i*2+1]==1?1:ip7[i*2]==1?0:0; + end + for(Integer i=0;i<`INPUT/512;i=i+1) begin + pp9[i]=ip8[i*2+1]==1?1:ip8[i*2]==1?0:0; + end + + pp10=ip9[1]==1?1:ip9[0]==1?0:0; + ip10=ip9[1] | ip9[0]; + + result[0] = pp10; + let op9 = pp9[result[1:0]]; + result = {result[8:0],op9}; + let op8 = pp8[result[2:0]]; + result = {result[8:0],op8}; + let op7 = pp7[result[3:0]]; + result = {result[8:0],op7}; + let op6 = pp6[result[4:0]]; + result = {result[8:0],op6}; + let op5 = pp5[result[5:0]]; + result = {result[8:0],op5}; + let op4 = pp4[result[6:0]]; + result = {result[8:0],op4}; + let op3 = pp3[result[7:0]]; + result = {result[8:0],op3}; + let op2 = pp2[result[8:0]]; + result = {result[8:0],op2}; + let op1 = pp1[result[9:0]]; + result = {result[8:0],op1}; + return truncate(result); + endfunction + +method Bit#(irid) encode(Bit#(irpins) ip); + return fn_encoder(ip); +endmethod +endmodule + +(*synthesize*) +module mkSencoder(Ifc_encoder#(512)); + let ifc(); + mkencoder inst(ifc); + return ifc(); +endmodule + +endpackage diff --git a/src/peripherals/plic/plic.bsv b/src/peripherals/plic/plic.bsv index 0e94ee7..1f1661a 100644 --- a/src/peripherals/plic/plic.bsv +++ b/src/peripherals/plic/plic.bsv @@ -13,14 +13,17 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ package plic; import Vector::*; - //import defined_parameters::*; import defined_types::*; import ConfigReg::*; import Semi_FIFOF::*; import AXI4_Lite_Types::*; import BUtils ::*; import ConcatReg ::*; + import encoder ::*; `include "instance_defines.bsv" + +`define INTERRUPT_LEVELS 8 + // import ConfigReg::*; /*Platform level interrupt controller: Refer to RISC-V privilege spec-v-1.10 chapter 7 @@ -51,7 +54,8 @@ package plic; */ -interface Ifc_PLIC#(numeric type addr_width,numeric type word_size,numeric type no_of_ir_pins); +interface Ifc_PLIC#(numeric type addr_width,numeric type word_size,numeric type no_of_ir_pins, + numeric type no_of_ir_levels); interface Vector#(no_of_ir_pins,Ifc_global_interrupt) ifc_external_irq; interface Ifc_program_registers#(addr_width,word_size) ifc_prog_reg; method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; @@ -59,95 +63,36 @@ interface Ifc_PLIC#(numeric type addr_width,numeric type word_size,numeric type endinterface //(*conflict_free = "rl_prioritise, prog_reg"*) -module mkplic(Ifc_PLIC#(addr_width,word_size,no_of_ir_pins)) +module mkplic(Ifc_PLIC#(addr_width,word_size,no_of_ir_pins,no_of_ir_levels)) provisos( - Log#(no_of_ir_pins, priority_bits), + Log#(no_of_ir_pins, ir_bits), + Log#(no_of_ir_levels, priority_bits), Mul#(8,word_size,data_width), - Add#(1,priority_bits,x_priority_bits), - Add#(msb_priority,1,priority_bits), - Add#(msb_priority_bits,1,no_of_ir_pins), - Add#(b__, no_of_ir_pins, data_width), - Add#(c__, priority_bits, data_width), - Add#(a__, 8, no_of_ir_pins), - Add#(e__, 32, data_width), - Add#(g__, 32, no_of_ir_pins), - Add#(f__, 3, priority_bits), - Add#(d__, 5, priority_bits) + //Mul#(3,no_iterations,ir_bits), + Add#(1,ir_bits,x_ir_bits), + Add#(msb_ir_bits,1,ir_bits), + Add#(msb_ir_pins,1,no_of_ir_pins), + Add#(msb_priority_levels,1,no_of_ir_levels), + Add#(msb_priority_bits,1,priority_bits), + Add#(a__, no_of_ir_levels, data_width), + Add#(b__, ir_bits, data_width), + Add#(c__, no_of_ir_pins, 1024), + Add#(d__, ir_bits, 10), + Add#(f__, no_of_ir_levels, 1024), + Add#(g__, priority_bits, 10), + Add#(h__, no_of_ir_levels, 32), + Add#(e__, 32, data_width) + //Mul#(no_iterations, 3, ir_bits), ); let v_no_of_ir_pins = valueOf(no_of_ir_pins); - let v_priority_bits = valueOf(priority_bits); - let v_msb_priority_bits = valueOf(msb_priority_bits); - let v_msb_priority = valueOf(msb_priority); + let v_ir_bits = valueOf(ir_bits); + let v_msb_ir_bits = valueOf(msb_ir_bits); + let v_msb_ir_pins = valueOf(msb_ir_pins); + let v_msb_priority = valueOf(msb_priority_levels); let v_data_width = valueOf(data_width); //(* noinline *) - /* This function defines the working of priority encoder with 4 bit inputs */ - function Bit#(8) priority_encoder(Bit#(8) inp, Bool alu_free); - Bit#(8) outp = 0; - if(alu_free) begin - if(inp[0]==1) - outp[0] = 1'b1; - else if(inp[1]==1) - outp[1] = 1'b1; - else if(inp[2]==1) - outp[2] = 1'b1; - else if(inp[3]==1) - outp[3] = 1'b1; - else if(inp[4]==1) - outp[4] = 1'b1; - else if(inp[5]==1) - outp[5] = 1'b1; - else if(inp[6]==1) - outp[6] = 1'b1; - else if(inp[7]==1) - outp[7] = 1'b1; - end - - return outp; - endfunction - - function bit any_req(Bit#(8) inp); - return inp[0] | inp[1] | inp[2] | inp[3] | inp[4] | inp[5] | inp[6] | inp[7]; - endfunction - - /* Encodes the grant vector */ - function Bit#(x_priority_bits) encoder(Bit#(no_of_ir_pins) inp); - Bit#(priority_bits) outp = 0; - bit outp_valid = 1'b1; - for(Integer i = 0; i < v_no_of_ir_pins; i = i+1) begin - if(inp[i]==1) - outp = fromInteger(i); - end - return {outp_valid,outp}; - endfunction - - function Reg#(t) readOnlyReg(t r); - return (interface Reg; - method t _read = r; - method Action _write(t x) = noAction; - endinterface); - endfunction - - /* Request vectors are passed down the tree and the grants are given back */ - function Bit#(no_of_ir_pins) encoder_tree(Bit#(no_of_ir_pins) inp); - Bit#(no_of_ir_pins) outp = 0; - //request to root - Bit#(8) root_reqs; - - //grant from root - Bit#(8) root_grants; - - for(Integer i=0;i<8;i=i+1) - root_reqs[i] = any_req(inp[8*fromInteger(i)+7:8*fromInteger(i)]); - - root_grants = priority_encoder(root_reqs, True); - - //grants are passed back to leaves - for(Integer i=0;i<8;i=i+1) - outp[8*fromInteger(i)+7:8*fromInteger(i)] = priority_encoder(inp[8*fromInteger(i)+7:8*fromInteger(i)], unpack(root_grants[i])); - return outp; - endfunction Vector#(no_of_ir_pins,Array#(Reg#(Bool))) rg_ip <- replicateM(mkCReg(2,False)); Reg#(Bool) rg_ie[v_no_of_ir_pins]; @@ -156,57 +101,117 @@ module mkplic(Ifc_PLIC#(addr_width,word_size,no_of_ir_pins)) rg_ie[i] = readOnlyReg(True); else rg_ie[i] <- mkReg(False); - Reg#(Bit#(32)) rg_priority_low[v_no_of_ir_pins]; + Reg#(Bit#(no_of_ir_levels)) rg_priority_low[v_no_of_ir_pins]; for(Integer i =0; i < v_no_of_ir_pins; i=i+1) if(i==28 || i == 29) - rg_priority_low[i] = readOnlyReg(32'h00000001); + rg_priority_low[i] = readOnlyReg(1); else rg_priority_low[i] <- mkConfigReg(0); - Reg#(Bit#(no_of_ir_pins)) rg_priority[v_no_of_ir_pins]; + Reg#(Bit#(32)) rg_priority[v_no_of_ir_pins]; for(Integer i=0;i < v_no_of_ir_pins;i=i+1) rg_priority[i] = concatReg2(readOnlyReg(0), rg_priority_low[i]); - Reg#(Bit#(5)) rg_priority_threshold_low <- mkReg(0); - Reg#(Bit#(priority_bits)) rg_priority_threshold = concatReg2(readOnlyReg(0),rg_priority_threshold_low); - Reg#(Bit#(priority_bits)) rg_interrupt_id <- mkConfigReg(0); + Reg#(Bit#(no_of_ir_levels)) rg_priority_threshold <- mkReg(0); + Reg#(Bit#(ir_bits)) rg_interrupt_id <- mkConfigReg(0); Reg#(Bool) rg_interrupt_valid <- mkConfigReg(False); - Reg#(Maybe#(Bit#(priority_bits))) rg_completion_id <- mkReg(tagged Invalid); + Reg#(Maybe#(Bit#(ir_bits))) rg_completion_id <- mkReg(tagged Invalid); + Reg#(Bit#(no_of_ir_pins)) rg_total_priority <- mkReg(0); + Reg#(Bit#(1)) rg_plic_state <- mkReg(0); //TODO put an enum later + Reg#(Bit#(no_of_ir_levels)) rg_winner_priority <- mkReg(0); + Ifc_encoder#(no_of_ir_levels) ir_priority_encoder <- mkencoder(); + Ifc_encoder#(no_of_ir_pins) irencoder <- mkencoder(); - rule rl_prioritise; + rule rl_prioritise(rg_plic_state==0); Bit#(priority_bits) winner_priority = 0; - Bit#(priority_bits) winner_interrupts = 0; - Bit#(x_priority_bits) ir_id_valid = 0; - Bit#(no_of_ir_pins) lv_priority = 0; + Bit#(ir_bits) winner_interrupts = 0; + Bit#(x_ir_bits) ir_id_valid = 0; + Bit#(no_of_ir_levels) lv_priority = 0; Bit#(no_of_ir_pins) lv_total_priority = 0; for(Integer i = 0; i < v_no_of_ir_pins; i = i + 1) begin if(rg_ip[i][1] && rg_ie[i]) begin - lv_priority = lv_priority | rg_priority[i]; - winner_interrupts = fromInteger(i); + lv_priority = lv_priority | truncate(rg_priority[i]); `ifdef verbose $display($time,"\tInterrupt id %d and priority is %d", i, lv_priority);`endif end end - winner_priority = encoder(encoder_tree(lv_priority))[v_msb_priority:0]; + winner_priority = ir_priority_encoder.encode(lv_priority); `ifdef verbose $display($time,"\t winner priority is %d", winner_priority);`endif for(Integer i = 0; i < v_no_of_ir_pins; i = i + 1) begin if(rg_priority[i][winner_priority] == 1 && rg_ip[i][1] && rg_ie[i]) lv_total_priority[i] = 1; end - if(lv_total_priority!=0) - winner_interrupts = encoder(encoder_tree(lv_total_priority))[v_msb_priority:0]; - if(winner_interrupts!=0) begin - ir_id_valid = encoder(rg_priority[winner_interrupts]); - if(winner_priority <= rg_priority_threshold) - begin - - `ifdef verbose $display("Interrupt valid");`endif - rg_interrupt_id <= winner_interrupts; - rg_interrupt_valid <= True; - $display($time,"\t The highest priority interrupt is %d and the priority is ", winner_interrupts, winner_priority); - end + if(lv_total_priority!=0) begin + rg_total_priority <= lv_total_priority; + rg_plic_state <= 1; + Bit#(no_of_ir_levels) lv_winner_priority = 0; + lv_winner_priority[winner_priority] = 1; + rg_winner_priority <= lv_winner_priority; end endrule + rule rl_encoder(rg_plic_state==1); + Bit#(ir_bits) interrupt_id = irencoder.encode(rg_total_priority); + if(interrupt_id!=0 && rg_priority_threshold >= rg_winner_priority) begin + `ifdef verbose $display("Interrupt valid");`endif + rg_interrupt_id <= interrupt_id; + rg_interrupt_valid <= True; + $display($time,"\t The highest priority interrupt is %d and the priority is ", interrupt_id, rg_winner_priority); + end + rg_plic_state <= 0; + + + //if(lv_total_priority!=0) + //winner_interrupts = encoder(encoder_tree(lv_total_priority))[v_msb_priority:0]; + //if(winner_interrupts!=0) begin + // if(winner_priority <= rg_priority_threshold) + // begin + // + // `ifdef verbose $display("Interrupt valid");`endif + // rg_interrupt_id <= winner_interrupts; + // rg_interrupt_valid <= True; + // $display($time,"\t The highest priority interrupt is %d and the priority is ", winner_interrupts, winner_priority); + // end + //end + endrule + + + //for(Integer i = 0; i> 2; if(mem_req.ld_st == Load) begin - source_id = address[v_msb_priority:0]; + source_id = address[v_msb_ir_bits:0]; `ifdef verbose $display($time,"\tPLIC : source %d Priority set to %h", source_id, mem_req.write_data);`endif data_return = zeroExtend(rg_priority[source_id]); end else if(mem_req.ld_st == Store) begin - Bit#(no_of_ir_pins) store_data; + Bit#(data_width) store_data; if(mem_req.byte_offset==0) - store_data=mem_req.write_data[v_msb_priority_bits:0]; + store_data=mem_req.write_data[v_msb_ir_pins:0]; else store_data=mem_req.write_data[v_data_width-1:v_data_width-v_no_of_ir_pins]; mem_req.byte_offset = mem_req.byte_offset >> 2; - source_id = address[v_msb_priority:0] | zeroExtend(mem_req.byte_offset); + source_id = address[v_msb_ir_bits:0]; $display($time,"\tPLIC : source %d Priority set to %h", source_id, store_data); - rg_priority[source_id] <= store_data; + rg_priority[source_id] <= truncate(store_data); end end - //else if(address < 'h0C002000) begin - else if(address<`PLICBase+'h2000)begin + else if(address < 'h0C002000) begin if(mem_req.ld_st == Load) begin - source_id = address[v_msb_priority:0]; + source_id = address[v_msb_ir_bits:0]; source_id = source_id << 3; for(Integer i = 0; i < 8; i = i+1) data_return[i] = pack(rg_ip[source_id + fromInteger(i)][1]); end else if(mem_req.ld_st == Store) begin - source_id = zeroExtend(mem_req.byte_offset); + source_id = address[v_msb_ir_bits:0]; source_id = source_id << 3; for(Integer i = 0; i < 8; i = i+1) begin `ifdef verbose $display($time,"\tPLIC : pending interrupt %b id %d", mem_req.write_data[i], source_id);`endif @@ -268,17 +271,16 @@ interface ifc_prog_reg = interface Ifc_program_registers; end end end - //else if(address < 'h0C020000) begin - else if(address < `PLICBase+'h20000)begin + else if(address < 'h0C020000) begin if(mem_req.ld_st == Load) begin - source_id = address[v_msb_priority:0]; + source_id = address[v_msb_ir_bits:0]; source_id = source_id << 3; for(Integer i = 0; i < 8; i = i+1) data_return[i] = pack(rg_ie[source_id + fromInteger(i)]); `ifdef verbose $display($time,"PLIC: Printing Source Enable Interrupt: %h data_return: %h",source_id,data_return); `endif end else if(mem_req.ld_st == Store) begin - source_id = zeroExtend(mem_req.byte_offset); + source_id = address[v_msb_ir_bits:0]; source_id = source_id << 3; for(Integer i = 0; i < 8; i = i+1) begin `ifdef verbose $display($time,"\tPLIC : enabled interrupt %b id %d", mem_req.write_data[i], source_id);`endif @@ -286,23 +288,21 @@ interface ifc_prog_reg = interface Ifc_program_registers; end end end - // else if(address == 'hC200000) begin - else if(address ==`PLICBase+'h200000)begin + else if(address == 'hC200000) begin if(mem_req.ld_st == Load) begin data_return = zeroExtend(rg_priority_threshold); end else if(mem_req.ld_st == Store) rg_priority_threshold <= mem_req.write_data[v_msb_priority:0]; end - // else if(address == 'hC200004) begin - else if(address == `PLICBase+'h200004)begin + else if(address == 'hC200004) begin if(mem_req.ld_st == Load) begin data_return = zeroExtend(rg_interrupt_id); rg_ip[rg_interrupt_id][1] <= False; `ifdef verbose $display($time,"rg_ip is made false here"); `endif end else if(mem_req.ld_st == Store) begin - source_id = mem_req.write_data[v_msb_priority:0]; + source_id = mem_req.write_data[v_msb_ir_bits:0]; rg_completion_id <= tagged Valid source_id; `ifdef verbose $display("rg_completion_id is made tagged valid and completion is signaled-- source_id: %d",source_id); `endif end @@ -339,7 +339,7 @@ endinterface module mkplicperipheral(Ifc_PLIC_AXI); AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_plic <- mkAXI4_Lite_Slave_Xactor; -Ifc_PLIC#(`PADDR, `DCACHE_WORD_SIZE, `INTERRUPT_PINS) plic <- mkplic(); +Ifc_PLIC#(`PADDR, `DCACHE_WORD_SIZE, `INTERRUPT_PINS, `INTERRUPT_LEVELS) plic <- mkplic(); (*preempts="rl_config_plic_reg_read, rl_config_plic_reg_write"*) rule rl_config_plic_reg_write; @@ -362,11 +362,12 @@ Ifc_PLIC#(`PADDR, `DCACHE_WORD_SIZE, `INTERRUPT_PINS) plic <- mkplic(); let ar <- pop_o(s_xactor_plic.o_rd_addr); let x <- plic.ifc_prog_reg.prog_reg(UncachedMemReq{address : ar.araddr, transfer_size : 'd3, u_signed : 0, byte_offset : 0, ld_st : Load}); -// if(ar.arsize==3'd0) -// x = duplicate(x[7:0]); -// else if(ar.arsize==3'd1) -// x = duplicate(x[15:0]); -// else if(ar.arsize==3'd2) + if(ar.arsize==3'd0) + x = duplicate(x[7:0]); + else if(ar.arsize==3'd1) + x = duplicate(x[15:0]); + else if(ar.arsize==3'd2) + x = duplicate(x[7:0]); let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(x), ruser: 0}; s_xactor_plic.i_rd_data.enq(r); -- 2.30.2 From a30dd6bb25eea95e9175346f97b00f85a01e17a5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 12:49:27 +0100 Subject: [PATCH 07/16] convert sdram to get/put --- src/peripherals/sdram/sdr_top.bsv | 132 ++++++++++++++++++------------ 1 file changed, 81 insertions(+), 51 deletions(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index ec1d821..373fc9f 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -49,19 +49,20 @@ import FIFOF::*; import Clocks::*; interface Ifc_sdram_out; - (*always_enabled,always_ready*) - method Action ipad_sdr_din(Bit#(64) pad_sdr_din); - method Bit#(9) sdram_sdio_ctrl(); - method Bit#(64) osdr_dout(); - method Bit#(8) osdr_den_n(); - method Bool osdr_cke(); - method Bool osdr_cs_n(); - method Bool osdr_ras_n (); - method Bool osdr_cas_n (); - method Bool osdr_we_n (); - method Bit#(8) osdr_dqm (); - method Bit#(2) osdr_ba (); - method Bit#(13) osdr_addr (); + (*always_enabled, always_ready*) + interface Put#(Bit#(64)) ipad_sdr_din; + interface Get#(Bit#(64)) osdr_dout; + interface Get#(Bit#(64)) osdr_den_n; + interface Get#(Bit#(1)) osdr_cke; + interface Get#(Bit#(1)) osdr_cs_n; + interface Get#(Bit#(1)) osdr_ras_n; + interface Get#(Bit#(1)) osdr_cas_n; + interface Get#(Bit#(1)) osdr_we_n; + interface Get#(Bit#(8)) osdr_dqm; + interface Get#(Bit#(2)) osdr_ba; + interface Get#(Bit#(13)) osdr_addr; + + method Bit#(9) sdram_sdio_ctrl; interface Clock sdram_clk; endinterface @@ -759,51 +760,80 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface Ifc_sdram_out ifc_sdram_out; - method Action ipad_sdr_din(Bit#(64) pad_sdr_din); - sdr_cntrl.ipad_sdr_din(pad_sdr_din); - endmethod - method Bit#(9) sdram_sdio_ctrl(); - return rg_cfg_sdio_ctrl; - endmethod - method Bit#(64) osdr_dout(); - return sdr_cntrl.osdr_dout(); - endmethod - method Bit#(8) osdr_den_n(); - return sdr_cntrl.osdr_den_n(); - endmethod - method Bool osdr_cke(); - return sdr_cntrl.osdr_cke(); - endmethod - - method Bool osdr_cs_n(); - return sdr_cntrl.osdr_cs_n(); - endmethod - - method Bool osdr_ras_n (); - return sdr_cntrl.osdr_ras_n; - endmethod - - method Bool osdr_cas_n (); - return sdr_cntrl.osdr_cas_n; - endmethod - - method Bool osdr_we_n (); - return sdr_cntrl.osdr_we_n; - endmethod + interface ipad_sdr_din = interface Put + method Action put(Bit#(64) in) + sdr_cntrl.ipad_sdr_din <= in; + endmethod + endinterface; - method Bit#(8) osdr_dqm (); + interface osdr_dout = interface Get + method ActionValue#(Bit#(64)) get; + return sdr_cntrl.osdr_dout(); + endmethod + endinterface; + + interface osdr_den_n = interface Get + method ActionValue#(Bit#(64)) get; + Bit#(64) temp; + for (int i=0; i<8; i=i+1) begin + temp[i*8] = sdr_cntrl.osdr_den_n[i]; + end + return temp; + endmethod + endinterface; + + interface osdr_cke = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cke()); + endmethod + endinterface; + + interface osdr_cs_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cs_n()); + endmethod + endinterface; + + interface osdr_ras_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_ras_n); + endmethod + endinterface; + + interface osdr_cas_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_cas_n); + endmethod + endinterface; + + interface osdr_we_n = interface Get + method ActionValue#(Bit#(1)) get; + return pack(sdr_cntrl.osdr_we_n); + endmethod + endinterface; + + interface osdr_dqm = interface Get + method ActionValue#(Bit#(8)) get; return sdr_cntrl.osdr_dqm; - endmethod + endmethod + endinterface; - method Bit#(2) osdr_ba (); + interface osdr_ba = interface Get + method ActionValue#(Bit#(2)) get; return sdr_cntrl.osdr_ba; - endmethod + endmethod + endinterface; - method Bit#(13) osdr_addr (); + interface osdr_addr = interface Get + method ActionValue#(Bit#(13)) get; return sdr_cntrl.osdr_addr; - endmethod - + endmethod + endinterface; + interface sdram_clk = clk0; + method Bit#(9) sdram_sdio_ctrl(); + return rg_cfg_sdio_ctrl; + endmethod endinterface -- 2.30.2 From a7993cb82c32376d4edbca9a099cbf071cf5ff93 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 13:38:41 +0100 Subject: [PATCH 08/16] move clk and cfg --- src/peripherals/sdram/sdr_top.bsv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index 373fc9f..181f6de 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -62,14 +62,14 @@ interface Ifc_sdram_out; interface Get#(Bit#(2)) osdr_ba; interface Get#(Bit#(13)) osdr_addr; - method Bit#(9) sdram_sdio_ctrl; - interface Clock sdram_clk; endinterface interface Ifc_sdr_slave; interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_sdram; interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_cntrl_reg; interface Ifc_sdram_out ifc_sdram_out; + method Bit#(9) sdram_sdio_ctrl; + interface Clock sdram_clk; endinterface typedef enum{ @@ -830,12 +830,12 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); endmethod endinterface; - interface sdram_clk = clk0; - method Bit#(9) sdram_sdio_ctrl(); - return rg_cfg_sdio_ctrl; - endmethod endinterface + interface sdram_clk = clk0; + method Bit#(9) sdram_sdio_ctrl(); + return rg_cfg_sdio_ctrl; + endmethod interface axi4_slave_sdram = s_xactor_sdram.axi_side; interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side; -- 2.30.2 From 921380942b9615baa3d296784b7d22b8b0d35419 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 07:21:42 +0100 Subject: [PATCH 09/16] add osdr_clock, remove unneeded SDIO ctrl / config, to be done by hand --- src/peripherals/sdram/sdr_top.bsv | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index 181f6de..1ab55e4 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -31,7 +31,6 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND `define SDR_INIT_DONE 8'h58 `define SDR_WIDTH 8'h60 `define SDR_COLBITS 8'h68 -`define SDR_SDIO_CTRL 8'h70 `define SDR_CLK_DELAY 8'h78 `define verbose @@ -61,6 +60,7 @@ interface Ifc_sdram_out; interface Get#(Bit#(8)) osdr_dqm; interface Get#(Bit#(2)) osdr_ba; interface Get#(Bit#(13)) osdr_addr; + interface Get#(Bit#(1)) osdr_clock; endinterface @@ -68,8 +68,6 @@ interface Ifc_sdr_slave; interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_sdram; interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_cntrl_reg; interface Ifc_sdram_out ifc_sdram_out; - method Bit#(9) sdram_sdio_ctrl; - interface Clock sdram_clk; endinterface typedef enum{ @@ -266,7 +264,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); Reg#(Bit#(4)) rg_cfg_sdr_twr_d <- mkConfigReg(4'h1,clocked_by clk0, reset_by rst0); Reg#(Bit#(2)) rg_cfg_sdr_width <- mkConfigReg(2'b0,clocked_by clk0, reset_by rst0); Reg#(Bit#(2)) rg_cfg_colbits <- mkConfigReg(2'b01,clocked_by clk0, reset_by rst0); - Reg#(Bit#(9)) rg_cfg_sdio_ctrl <- mkConfigReg(9'b000100011,clocked_by clk0, reset_by rst0); Reg#(Bit#(8)) rg_cfg_sdr_clk_delay <- mkConfigReg(8'b00001000,clocked_by clk0, reset_by rst0); Reg#(Bit#(`SDR_RFSH_TIMER_W )) rg_cfg_sdr_rfsh <- mkConfigReg(12'h100,clocked_by clk0, reset_by rst0); @@ -373,7 +370,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); `SDR_COLBITS : rg_cfg_colbits <= data [1:0]; - `SDR_SDIO_CTRL : rg_cfg_sdio_ctrl <= data [8:0]; `SDR_CLK_DELAY : rg_cfg_sdr_clk_delay <= data [7:0]; @@ -414,7 +410,6 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); `SDR_COLBITS : return extend(rg_cfg_colbits); - `SDR_SDIO_CTRL : return extend(rg_cfg_sdio_ctrl); `SDR_CLK_DELAY : return extend(rg_cfg_sdr_clk_delay); @@ -830,13 +825,13 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); endmethod endinterface; + interface osdr_clock = interface Get + method ActionValue#(Bit#(1)) get; + return ?; + endmethod + endinterface; endinterface - interface sdram_clk = clk0; - method Bit#(9) sdram_sdio_ctrl(); - return rg_cfg_sdio_ctrl; - endmethod - interface axi4_slave_sdram = s_xactor_sdram.axi_side; interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side; -- 2.30.2 From b95805717facb0fdab0a64bbe205b7157976c77b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 10:20:31 +0100 Subject: [PATCH 10/16] missing semicolon --- src/peripherals/sdram/sdr_top.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index 1ab55e4..cc3e0b0 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -756,7 +756,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface Ifc_sdram_out ifc_sdram_out; interface ipad_sdr_din = interface Put - method Action put(Bit#(64) in) + method Action put(Bit#(64) in); sdr_cntrl.ipad_sdr_din <= in; endmethod endinterface; -- 2.30.2 From 999a00cb651c843fe869eb954f28b14e7329c7f2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 10:24:12 +0100 Subject: [PATCH 11/16] add get/put --- src/peripherals/sdram/sdr_top.bsv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index cc3e0b0..20e6964 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -36,6 +36,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND package sdr_top; +import GetPut:: *; import Semi_FIFOF :: *; import AXI4_Types :: *; import AXI4_Fabric :: *; -- 2.30.2 From 7004da9cf8a7a568870259bac005245a8e1ff6f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 10:28:47 +0100 Subject: [PATCH 12/16] assign in --- src/peripherals/sdram/sdr_top.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index 20e6964..56677f8 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -758,7 +758,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface ipad_sdr_din = interface Put method Action put(Bit#(64) in); - sdr_cntrl.ipad_sdr_din <= in; + sdr_cntrl.ipad_sdr_din(in); endmethod endinterface; -- 2.30.2 From dac2798fce0a2725494051e363f870b4a7cc6dc0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 10:30:38 +0100 Subject: [PATCH 13/16] assign zero to temp --- src/peripherals/sdram/sdr_top.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index 56677f8..d886fd5 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -770,7 +770,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface osdr_den_n = interface Get method ActionValue#(Bit#(64)) get; - Bit#(64) temp; + Bit#(64) temp = 0; for (int i=0; i<8; i=i+1) begin temp[i*8] = sdr_cntrl.osdr_den_n[i]; end -- 2.30.2 From 4281aa9ba88cb0aea5efef17ff324ca0ffac86fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 12:32:01 +0100 Subject: [PATCH 14/16] add dummy clock register for now --- src/peripherals/sdram/sdr_top.bsv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index d886fd5..781dd76 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -245,10 +245,8 @@ endfunction (*synthesize*) -module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); +module mksdr_axi4_slave#(Clock clk0, Reset rst0) (Ifc_sdr_slave); - Reset rst0 <- mkAsyncResetFromCR (0, clk0); - Reg#(Bit#(9)) rg_delay_count <- mkReg(0,clocked_by clk0, reset_by rst0); Reg#(Bit#(9)) rg_rd_actual_len <- mkReg(0,clocked_by clk0, reset_by rst0); Reg#(bit) rg_app_req <- mkDReg(0,clocked_by clk0, reset_by rst0); @@ -341,6 +339,9 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_cntrl_reg <- mkAXI4_Slave_Xactor; Ifc_sdram sdr_cntrl <- mksdrc_top(clocked_by clk0, reset_by rst0); + // TODO remove the following when clock to bit type conversion is done + Reg#(Bit#(1)) rg_dummy <- mkReg(0, clocked_by clk0, reset_by rst0); + function Action fn_wr_cntrl_reg(Bit#(64) data, Bit#(8) address); action case(address) @@ -828,7 +829,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface osdr_clock = interface Get method ActionValue#(Bit#(1)) get; - return ?; + return rg_dummy; endmethod endinterface; endinterface -- 2.30.2 From a7c04b8f08bc5c0bfb4241efb273a0b9deb01141 Mon Sep 17 00:00:00 2001 From: Neel Date: Fri, 3 Aug 2018 10:16:28 +0530 Subject: [PATCH 15/16] providing default values of the mux to be compile time defined --- src/peripherals/mux/mux.bsv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/peripherals/mux/mux.bsv b/src/peripherals/mux/mux.bsv index d7ff5f6..39c48fa 100644 --- a/src/peripherals/mux/mux.bsv +++ b/src/peripherals/mux/mux.bsv @@ -35,11 +35,13 @@ package mux; endinterface // (*synthesize*) - module mkmux(MUX#(ionum_)); - Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg <-replicateM(mkConfigReg(0)); + module mkmux#(Bit#(TMul#(ionum_, 2)) defvalue)(MUX#(ionum_)); + let ionum=valueOf(ionum_); + Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg + for(Integer i=0;i Date: Fri, 3 Aug 2018 10:40:29 +0530 Subject: [PATCH 16/16] missing semicolon added --- src/peripherals/mux/mux.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/peripherals/mux/mux.bsv b/src/peripherals/mux/mux.bsv index 39c48fa..d1acd93 100644 --- a/src/peripherals/mux/mux.bsv +++ b/src/peripherals/mux/mux.bsv @@ -37,7 +37,7 @@ package mux; // (*synthesize*) module mkmux#(Bit#(TMul#(ionum_, 2)) defvalue)(MUX#(ionum_)); let ionum=valueOf(ionum_); - Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg + Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg ; for(Integer i=0;i