| 2019-07-02 |
Alain Péteut | build.plat: add iter_extra_files method.
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commit | commitdiff | tree |
| 2019-07-02 |
whitequark | back.rtlil: emit \sig$next wires instead of \$next...
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commit | commitdiff | tree |
| 2019-07-02 |
whitequark | back.rtlil: do not emit $next wires for comb signals.
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commit | commitdiff | tree |
| 2019-07-02 |
whitequark | hdl.rec: implement slicing by component names.
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commit | commitdiff | tree |
| 2019-07-02 |
whitequark | hdl.rec: implement Record.like.
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commit | commitdiff | tree |
| 2019-07-02 |
Alain Péteut | vendor.xilinx_7series: read extra .xdc files.
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commit | commitdiff | tree |
| 2019-07-01 |
whitequark | hdl.mem: use read_port(domain="comb") for asynchronous...
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commit | commitdiff | tree |
| 2019-07-01 |
whitequark | back.rtlil: fix Array regression in 32446831.
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | back.pysim: create unique ResetSynchronizer internal...
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | back.pysim: override ResetSynchronizer implementation.
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | lib.cdc: avoid interior clock domains in ResetSynchronizer.
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | lib.cdc: eliminate no_retiming attributes.
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | vendor.lattice_ice40: fix instance of negedge FF due...
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commit | commitdiff | tree |
| 2019-06-28 |
Alain Péteut | build.plat: fix dedent overrides.
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | README: tone down the instability warning to reflect...
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case...
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commit | commitdiff | tree |
| 2019-06-28 |
whitequark | hdl.ir, back.rtlil: allow specifying attributes on...
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commit | commitdiff | tree |
| 2019-06-27 |
whitequark | examples: add concise UART example.
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commit | commitdiff | tree |
| 2019-06-26 |
whitequark | back.pysim: fix scope screwup.
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commit | commitdiff | tree |
| 2019-06-25 |
whitequark | compat.fhdl.structure: fix typo.
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commit | commitdiff | tree |
| 2019-06-25 |
whitequark | compat.fhdl.structure: simplify handling of default...
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commit | commitdiff | tree |
| 2019-06-25 |
whitequark | hdl.{ast,dst}: directly represent RTLIL default case.
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commit | commitdiff | tree |
| 2019-06-25 |
whitequark | vendor.xilinx_{spartan6,7series}: speedgrade→speed.
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commit | commitdiff | tree |
| 2019-06-25 |
whitequark | vendor.lattice_ecp5: implement.
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commit | commitdiff | tree |
| 2019-06-19 |
whitequark | vendor.lattice_ice40: use different --package for 4k...
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commit | commitdiff | tree |
| 2019-06-17 |
Jean-François Nguyen | vendor.xilinx_7series: fix IOB packing.
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commit | commitdiff | tree |
| 2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
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commit | commitdiff | tree |
| 2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: cleanup. NFC.
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commit | commitdiff | tree |
| 2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: connect FCDE and...
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commit | commitdiff | tree |
| 2019-06-16 |
Alain Péteut | build.plat: dedent overrides.
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commit | commitdiff | tree |
| 2019-06-14 |
whitequark | vendor.lattice_ice40: never place an inverter on global...
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commit | commitdiff | tree |
| 2019-06-13 |
Jean-François Nguyen | vendor.xilinx_7series: implement inverters.
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commit | commitdiff | tree |
| 2019-06-13 |
Jean-François Nguyen | vendor.xilinx_spartan6: implement DDR I/O buffers and...
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commit | commitdiff | tree |
| 2019-06-13 |
whitequark | compat.fhdl.structure: fix Case().makedefault().
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commit | commitdiff | tree |
| 2019-06-13 |
whitequark | compat.fhdl.structure: always order default case as...
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commit | commitdiff | tree |
| 2019-06-13 |
whitequark | hdl.ast: tighten assertion in Switch().
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commit | commitdiff | tree |
| 2019-06-12 |
whitequark | Simplify code by using Signal.like(name_suffix=".....
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commit | commitdiff | tree |
| 2019-06-12 |
whitequark | hdl.ast: add name_suffix=".." option to Signal.like().
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commit | commitdiff | tree |
| 2019-06-12 |
Jean-François Nguyen | vendor.xilinx_7series: implement DDR I/O buffers.
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commit | commitdiff | tree |
| 2019-06-12 |
whitequark | vendor.lattice_ice40: fix typo.
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commit | commitdiff | tree |
| 2019-06-12 |
whitequark | build.{dsl,res,plat}: add PinsN and DiffPairsN.
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commit | commitdiff | tree |
| 2019-06-11 |
whitequark | hdl.ast: implement values with custom lowering.
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commit | commitdiff | tree |
| 2019-06-11 |
whitequark | back.pysim: check for a clock being added twice.
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commit | commitdiff | tree |
| 2019-06-11 |
whitequark | back.rtlil: mask memory init values.
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commit | commitdiff | tree |
| 2019-06-11 |
whitequark | hdl.mem: coerce memory init values to integers.
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commit | commitdiff | tree |
| 2019-06-09 |
Simon Kirkby | lib.cdc: fix typo.
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commit | commitdiff | tree |
| 2019-06-07 |
Jean-François Nguyen | vendor.xilinx_spartan6: implement.
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commit | commitdiff | tree |
| 2019-06-07 |
Jean-François Nguyen | vendor.xilinx_7series: fix typos.
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commit | commitdiff | tree |
| 2019-06-06 |
whitequark | build.dsl: fix precondition check in Pins.
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commit | commitdiff | tree |
| 2019-06-06 |
Jean-François Nguyen | vendor.xilinx_7series: implement.
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commit | commitdiff | tree |
| 2019-06-05 |
whitequark | build.res: allow querying frequency of a previously...
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commit | commitdiff | tree |
| 2019-06-05 |
whitequark | build.{dsl,res,plat}: apply clock constraints to signals...
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commit | commitdiff | tree |
| 2019-06-05 |
whitequark | build.dsl: replace extras= with Attrs().
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commit | commitdiff | tree |
| 2019-06-05 |
whitequark | Typos and style fixes. NFC.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | vendor.lattice_ice40: normalize device names.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | hdl.ir: rephrase elaboratable warning to not look like...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | compat.fhdl.module: silence "unused elaboratable" warnings.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering for TSTriple...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | compat.fhdl.module: implement some TODO'd deprecation...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.run: fix product extraction to work on Windows.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.plat: hide executed commands in quiet builds...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.plat: allow (easily) overriding with an empty...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | compat.fhdl.module: CompatModule should be elaboratable.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.res: use ConstraintError iff a constraint invariant...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | vendor.board: split off into nmigen-boards package.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.run: simplify using build products locally, e...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.res: simplify emission of port constraints on...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | Clean up imports.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | build.run: extract from build.plat.
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: clk16 pin does not have a...
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commit | commitdiff | tree |
| 2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: fix typo.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.conn.pmod: implement.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | examples: reorganize into examples/basic and examples...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.board: extract package.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.tinyfpga_bx: add connectors.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.icestick: add connectors.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.ice40_hx1k_blink_evn: add (some) connectors.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{plat,res}: add support for connectors.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.dsl: add support for connectors.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | compat.fhdl.specials: TSTriple is not an elaboratable.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential output...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential input...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement SDR and DDR I...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: add i_clk and o_clk to pin layout with xdr>=1.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.rec: unbreak hasattr(rec, ...).
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{dsl,plat,res}: allow dir="oe".
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: allow dir="oe".
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{res,plat}: use xdr=0 as default, not xdr=1.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.res: allow requesting raw ports, with dir="-".
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: allow Pin(xdr=0), representing a combinatorial...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: enable SystemVerilog when...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.res: if not specified, request resource #0.
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: instantiate SB_IO and apply...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.ir: accept LHS signals like slices as Instance...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.dsl: allow adding submodules with computed name...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.ir: accept expanded (kind, name, value) tuples...
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commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{res,plat}: propagate extras to pin fragment...
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commit | commitdiff | tree |
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