2019-06-28 |
whitequark | hdl.ir, back.rtlil: allow specifying attributes on...
|
commit | commitdiff | tree |
2019-06-27 |
whitequark | examples: add concise UART example.
|
commit | commitdiff | tree |
2019-06-26 |
whitequark | back.pysim: fix scope screwup.
|
commit | commitdiff | tree |
2019-06-25 |
whitequark | compat.fhdl.structure: fix typo.
|
commit | commitdiff | tree |
2019-06-25 |
whitequark | compat.fhdl.structure: simplify handling of default...
|
commit | commitdiff | tree |
2019-06-25 |
whitequark | hdl.{ast,dst}: directly represent RTLIL default case.
|
commit | commitdiff | tree |
2019-06-25 |
whitequark | vendor.xilinx_{spartan6,7series}: speedgrade→speed.
|
commit | commitdiff | tree |
2019-06-25 |
whitequark | vendor.lattice_ecp5: implement.
|
commit | commitdiff | tree |
2019-06-19 |
whitequark | vendor.lattice_ice40: use different --package for 4k...
|
commit | commitdiff | tree |
2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
|
commit | commitdiff | tree |
2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: cleanup. NFC.
|
commit | commitdiff | tree |
2019-06-17 |
whitequark | vendor.xilinx_{7series,spartan6}: connect FCDE and...
|
commit | commitdiff | tree |
2019-06-14 |
whitequark | vendor.lattice_ice40: never place an inverter on global...
|
commit | commitdiff | tree |
2019-06-13 |
whitequark | compat.fhdl.structure: fix Case().makedefault().
|
commit | commitdiff | tree |
2019-06-13 |
whitequark | compat.fhdl.structure: always order default case as...
|
commit | commitdiff | tree |
2019-06-13 |
whitequark | hdl.ast: tighten assertion in Switch().
|
commit | commitdiff | tree |
2019-06-12 |
whitequark | Simplify code by using Signal.like(name_suffix=".....
|
commit | commitdiff | tree |
2019-06-12 |
whitequark | hdl.ast: add name_suffix=".." option to Signal.like().
|
commit | commitdiff | tree |
2019-06-12 |
whitequark | vendor.lattice_ice40: fix typo.
|
commit | commitdiff | tree |
2019-06-12 |
whitequark | build.{dsl,res,plat}: add PinsN and DiffPairsN.
|
commit | commitdiff | tree |
2019-06-11 |
whitequark | hdl.ast: implement values with custom lowering.
|
commit | commitdiff | tree |
2019-06-11 |
whitequark | back.pysim: check for a clock being added twice.
|
commit | commitdiff | tree |
2019-06-11 |
whitequark | back.rtlil: mask memory init values.
|
commit | commitdiff | tree |
2019-06-11 |
whitequark | hdl.mem: coerce memory init values to integers.
|
commit | commitdiff | tree |
2019-06-06 |
whitequark | build.dsl: fix precondition check in Pins.
|
commit | commitdiff | tree |
2019-06-05 |
whitequark | build.res: allow querying frequency of a previously...
|
commit | commitdiff | tree |
2019-06-05 |
whitequark | build.{dsl,res,plat}: apply clock constraints to signals...
|
commit | commitdiff | tree |
2019-06-05 |
whitequark | build.dsl: replace extras= with Attrs().
|
commit | commitdiff | tree |
2019-06-05 |
whitequark | Typos and style fixes. NFC.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.lattice_ice40: normalize device names.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | hdl.ir: rephrase elaboratable warning to not look like...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.module: silence "unused elaboratable" warnings.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering for TSTriple...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.specials: fix platform lowering.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.module: implement some TODO'd deprecation...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.run: fix product extraction to work on Windows.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.plat: hide executed commands in quiet builds...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.plat: allow (easily) overriding with an empty...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | compat.fhdl.module: CompatModule should be elaboratable.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.res: use ConstraintError iff a constraint invariant...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.board: split off into nmigen-boards package.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.run: simplify using build products locally, e...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.res: simplify emission of port constraints on...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | Clean up imports.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | build.run: extract from build.plat.
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: clk16 pin does not have a...
|
commit | commitdiff | tree |
2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: fix typo.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.conn.pmod: implement.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | examples: reorganize into examples/basic and examples...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.board: extract package.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.tinyfpga_bx: add connectors.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.icestick: add connectors.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.ice40_hx1k_blink_evn: add (some) connectors.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{plat,res}: add support for connectors.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.dsl: add support for connectors.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | compat.fhdl.specials: TSTriple is not an elaboratable.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential output...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential input...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement SDR and DDR I...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | lib.io: add i_clk and o_clk to pin layout with xdr>=1.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.rec: unbreak hasattr(rec, ...).
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{dsl,plat,res}: allow dir="oe".
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | lib.io: allow dir="oe".
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{res,plat}: use xdr=0 as default, not xdr=1.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: allow requesting raw ports, with dir="-".
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | lib.io: allow Pin(xdr=0), representing a combinatorial...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: enable SystemVerilog when...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: if not specified, request resource #0.
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: instantiate SB_IO and apply...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.ir: accept LHS signals like slices as Instance...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.dsl: allow adding submodules with computed name...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | hdl.ir: accept expanded (kind, name, value) tuples...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.{res,plat}: propagate extras to pin fragment...
|
commit | commitdiff | tree |
2019-06-03 |
whitequark | build.res: simplify. NFC.
|
commit | commitdiff | tree |
2019-06-02 |
whitequark | build.dsl: require a dict for extras instead of a stringly...
|
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.fpga.lattice_ice40: use .bin suffix for bitstream...
|
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.tinyfpga_{b→bx}
|
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.tinyfpga_b: fix IO_STANDARD.
|
commit | commitdiff | tree |
2019-06-02 |
whitequark | vendor.icestick: fix typo.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | Travis: update install script.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.ice40_hx1k_blink_evn: implement.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.icestick: implement.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | vendor.fpga.lattice_ice40: implement.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.plat: implement.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.res: always return a Pin record.
|
commit | commitdiff | tree |
2019-06-01 |
whitequark | build.res: accept a list of clocks in ConstraintManager...
|
commit | commitdiff | tree |
2019-05-26 |
whitequark | back.rtlil: allow specifying platform for convert().
|
commit | commitdiff | tree |
2019-05-26 |
whitequark | Add versioneer.
|
commit | commitdiff | tree |
2019-05-26 |
whitequark | hdl.ir: silence unused elaboratable warning on interpreter...
|
commit | commitdiff | tree |
2019-05-25 |
whitequark | build.dsl: make Pins and DiffPairs iterable.
|
commit | commitdiff | tree |
2019-05-25 |
whitequark | build.dsl: improve repr of Pins() and DiffPairs().
|
commit | commitdiff | tree |
2019-05-25 |
whitequark | hdl.rec: allow providing fields during construction.
|
commit | commitdiff | tree |
2019-05-25 |
whitequark | Consider Instances a part of containing fragment for...
|
commit | commitdiff | tree |
2019-05-15 |
whitequark | hdl.ir: when adding sync domain to a design, also add...
|
commit | commitdiff | tree |
2019-05-13 |
whitequark | hdl.ir: during port propagation, defs should take priority...
|
commit | commitdiff | tree |
2019-05-13 |
whitequark | back.rtlil: assign undriven signals to their reset...
|
commit | commitdiff | tree |
2019-05-12 |
whitequark | hdl: make all public Value classes other than Record...
|
commit | commitdiff | tree |
2019-05-12 |
whitequark | hdl.ir: only pull explicitly specified ports to toplevel...
|
commit | commitdiff | tree |
next |