| 2019-08-23 |
whitequark | back.pysim: implement sim.add_clock(if_exists=True).
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commit | commitdiff | tree |
| 2019-08-23 |
whitequark | back.pysim: don't crash when trying to drive a nonexistent...
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commit | commitdiff | tree |
| 2019-08-23 |
whitequark | build.run: add BuildPlan.digest(), useful for caching.
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commit | commitdiff | tree |
| 2019-08-22 |
whitequark | vendor.lattice_ecp5: add Diamond support.
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commit | commitdiff | tree |
| 2019-08-22 |
whitequark | vendor: eliminate unnecessary LUT instantiation.
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commit | commitdiff | tree |
| 2019-08-22 |
Reto Kramer | examples/basic/uart: document `divisor` parameter.
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commit | commitdiff | tree |
| 2019-08-22 |
whitequark | back.rtlil: print real parameters with maximum precision.
|
commit | commitdiff | tree |
| 2019-08-22 |
Darrell Harmon | back.rtlil: add support for real (float) parameters...
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commit | commitdiff | tree |
| 2019-08-21 |
Darrell Harmon | vendor.xilinx_series7: use STARTUPE2, not STARTUPE3.
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commit | commitdiff | tree |
| 2019-08-21 |
whitequark | vendor.lattice_ice40: remove `--placer heap` default...
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commit | commitdiff | tree |
| 2019-08-21 |
whitequark | vendor: style. NFC.
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commit | commitdiff | tree |
| 2019-08-21 |
whitequark | build.plat: remove TemplatedPlatform.unix_interpreter.
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commit | commitdiff | tree |
| 2019-08-21 |
whitequark | back.pysim: allow coroutines as processes.
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commit | commitdiff | tree |
| 2019-08-20 |
William D. Jones | test.test_examples: Convert pathlib-specific class...
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | back.verilog: parse output of `yosys -V`.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | Fix nmigen.__version__ to work on git-archive artifacts.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | build.plat, hdl.ir: coordinate missing domain creation.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | vendor.lattice_ice40: use a local clock domain in create_mis...
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | README: fix typos.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | hdl.cd: implement local clock domains.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | back.pysim: index domains by identity, not by name.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | hdl.xfrm: lower resets in DomainLowerer as well.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | hdl.xfrm: consider fragment's own domains in DomainLowerer.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | formal→asserts
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | tracer: fix typo.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | build.plat: do not prepare fragments twice.
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commit | commitdiff | tree |
| 2019-08-19 |
whitequark | back.{rtlil,verilog}: split convert_fragment() off...
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commit | commitdiff | tree |
| 2019-08-18 |
Robin Heinemann | build.dsl: add conn argument to Connector.
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commit | commitdiff | tree |
| 2019-08-18 |
whitequark | compat.fhdl.decorators: avoid using deprecated NativeCEInserter.
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commit | commitdiff | tree |
| 2019-08-18 |
whitequark | hdl.xfrm: make deprecated CEInserter more well-behaved.
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commit | commitdiff | tree |
| 2019-08-15 |
whitequark | hdl.ast: implement Initial.
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commit | commitdiff | tree |
| 2019-08-15 |
whitequark | hdl.xfrm: sample cache should be per-fragment.
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commit | commitdiff | tree |
| 2019-08-12 |
whitequark | hdl.xfrm: CEInserter→EnableInserter.
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commit | commitdiff | tree |
| 2019-08-08 |
whitequark | hdl.ast: hash-cons ValueKey.
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commit | commitdiff | tree |
| 2019-08-08 |
whitequark | tracer: use sys._getframe directly.
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commit | commitdiff | tree |
| 2019-08-08 |
whitequark | compat.fhdl.decorators: port from oMigen.
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commit | commitdiff | tree |
| 2019-08-08 |
whitequark | compat.fhdl.module: fix finalization of transformed...
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commit | commitdiff | tree |
| 2019-08-07 |
whitequark | vendor.lattice_ice40: add iCE5LP2K support.
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commit | commitdiff | tree |
| 2019-08-07 |
whitequark | vendor.lattice_ice40: add iCE40UP3K support.
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commit | commitdiff | tree |
| 2019-08-07 |
whitequark | vendor.lattice_ice40: add iCE5LP1K support.
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_{spartan_3_6,7series}: reconsider default...
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_spartan_3_6: reconsider bitgen defaults.
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_spartan_3_6: set bitgen defaults to ...
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_spartan_3_6: always use -w for map/par...
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_spartan_3_6: do not use retiming by default.
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.xilinx_spartan_3_6: force use of bash on UNIX.
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | build.plat: allow selecting a specific UNIX shell interpreter.
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | vendor.lattice_ice40: avoid routing conflicts with...
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commit | commitdiff | tree |
| 2019-08-04 |
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | back.rtlil: actually match shape of left hand side.
|
commit | commitdiff | tree |
| 2019-08-03 |
whitequark | vendor.lattice_ice40: add missing signal indexing.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | build.run: use keyword-only arguments where appropriate.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | compat.fhdl.specials: track changes in build.plat.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.dsl: reword m.If(~True) warning to be more clear.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | build.plat,vendor: automatically create sync domain...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: allow adding more than one domain in missing...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: don't expose as ports missing domains added...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | build.plat: add default_rst, to be used with default_clk.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | build.plat: add default_clk{,_constraint,_frequency}.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: allow returning elaboratables from missing...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: raise DomainError if a domain is used but not...
|
commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: call back from Fragment.prepare if a clock...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.dsl: warn on suspicious statements like `m.If(...
|
commit | commitdiff | tree |
| 2019-08-03 |
whitequark | Improve test added in 29fee01f to not leak warnings.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | back.rtlil: fix sim-synth mismatch with assigns following...
|
commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ast: fix typo.
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word...
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commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ast, back.rtlil: add source locations to anonymous...
|
commit | commitdiff | tree |
| 2019-08-03 |
whitequark | hdl.ir: warn if .elaborate() returns None.
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commit | commitdiff | tree |
| 2019-07-31 |
whitequark | hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
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commit | commitdiff | tree |
| 2019-07-21 |
N. Engelhardt | vendor: don't emit duplicate iobuf submodule names.
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commit | commitdiff | tree |
| 2019-07-19 |
N. Engelhardt | hdl.dsl: add getters to m.submodules.
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commit | commitdiff | tree |
| 2019-07-15 |
Alain Péteut | lib.fifo: fix typo.
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commit | commitdiff | tree |
| 2019-07-14 |
Staf Verhaegen | Pin: Add extra hierarchy level for name derivation
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commit | commitdiff | tree |
| 2019-07-14 |
William D. Jones | build.run: Ensure batch script returns proper error...
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commit | commitdiff | tree |
| 2019-07-12 |
whitequark | back.pysim: correctly add gtkwave traces for signals...
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commit | commitdiff | tree |
| 2019-07-10 |
William D. Jones | build.dsl: Add optional name_suffix to Resource.family.
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commit | commitdiff | tree |
| 2019-07-10 |
whitequark | back.pysim: avoid malformed VCD files when a decoder...
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commit | commitdiff | tree |
| 2019-07-10 |
whitequark | hdl.ir: make UnusedElaboratable a real warning.
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commit | commitdiff | tree |
| 2019-07-09 |
whitequark | back.rtlil: add decodings to cases when switching on...
|
commit | commitdiff | tree |
| 2019-07-09 |
whitequark | back.verilog: run proc_prune for much cleaner output.
|
commit | commitdiff | tree |
| 2019-07-09 |
whitequark | hdl.{ast,dsl},back.rtlil: track source locations for...
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commit | commitdiff | tree |
| 2019-07-09 |
Jacob Lifshay | tracer: add PyPy support to get_var_name().
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commit | commitdiff | tree |
| 2019-07-09 |
whitequark | build.dsl: add Resource.family abstraction.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | build.{dsl,res}: allow platform-dependent attributes...
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | hdl.rec: respect modifications to signals in Record...
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | back.rtlil: don't name-prefix signals connected to...
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | build.{dsl,res}: allow removing attributes from subsignals.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | build.dsl: allow assertions on subsignal widths.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | hdl.{ast,cd,dsl,xfrm}: reject inappropriately used...
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | test: fix Travis.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | test: generate examples to verilog as part of unit...
|
commit | commitdiff | tree |
| 2019-07-08 |
whitequark | examples/basic/ctr_ce: fix outdated syntax.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | compat.genlib.fsm: fix after commit dac62754.
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | hdl.xfrm: don't overwrite source locations on ClockDomain...
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commit | commitdiff | tree |
| 2019-07-08 |
whitequark | hdl.{dsl,mem,xfrm}: inject appropriate source locations.
|
commit | commitdiff | tree |
| 2019-07-08 |
whitequark | back.rtlil: ignore empty source locations.
|
commit | commitdiff | tree |
| 2019-07-08 |
whitequark | hdl.ast: use keyword-only arguments as appropriate.
|
commit | commitdiff | tree |
| 2019-07-08 |
whitequark | back.rtlil: attach source locations to switches, not...
|
commit | commitdiff | tree |
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