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2020-07-22	Jędrzej Boczar	test/axi: add crossbar stress tests	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/integration: add bus standard parser arguments	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/interconnect/axi: improve Timeout module and test...	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	test/axi: add shared AXI Lite interconnect tests	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/interconnect/axi: implement AXI Lite decoder	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/interconnect/axi: lock AXILiteArbiter until all...	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	test/test_axi: add AXI Lite interconnect arbiter tests	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	socinterconnect/axi: interconnect shared sketch	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/interconnect/axi: point-to-point interconnect and...	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/integration: choose interconnect based on bus standard	commit \| commitdiff \| tree
2020-07-22	Jędrzej Boczar	soc/integration: add axi-lite standard to SoCBusHandler	commit \| commitdiff \| tree
2020-07-20	Jędrzej Boczar	fix/Vivado: don't instantiate wishbone.Converter in...	commit \| commitdiff \| tree
2020-07-16	Jędrzej Boczar	soc/interconnect/axi: propagate response errors in...	commit \| commitdiff \| tree
2020-07-16	Jędrzej Boczar	soc/interconnect/axi: implement AXILite down-converter	commit \| commitdiff \| tree
2020-07-16	Jędrzej Boczar	soc/integration: revert `bus` argument for add_ram...	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	soc/integration: use AXILiteConverter (dummy implementation...	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	soc/interconnect/axi: add connect methods for convenience	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	test/axi: add AXILite2CSR and AXILiteSRAM tests	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	soc/interconnect/axi: improve SRAM/CSR access speed	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	soc/interconnect: add AXILite SRAM	commit \| commitdiff \| tree
2020-07-15	Jędrzej Boczar	soc/interconnect: add AXILite2CSR bridge	commit \| commitdiff \| tree
2020-07-14	Jędrzej Boczar	soc/integration: update add_adapter to convert between...	commit \| commitdiff \| tree
2020-06-24	Jędrzej Boczar	bios: move memtest from liblitedram to libbase	commit \| commitdiff \| tree
2020-05-29	Jędrzej Boczar	bios/litedram: add option to verify SPD EEPROM memory...	commit \| commitdiff \| tree
2020-05-29	Jędrzej Boczar	build/sim/spdeeprom: use hex format when loading from...	commit \| commitdiff \| tree
2020-05-28	Jędrzej Boczar	litex/build/sim: add module for simulating SPD EEPROM	commit \| commitdiff \| tree
2020-05-27	Jędrzej Boczar	bios: move I2C from liblitedram to libbase	commit \| commitdiff \| tree
2020-05-27	Jędrzej Boczar	bios/sdram: expose I2C functions	commit \| commitdiff \| tree
2020-05-21	Jędrzej Boczar	litex_sim: load SPD data from files in hexdump format...	commit \| commitdiff \| tree
2020-05-21	Jędrzej Boczar	bios/sdram: add BIOS command for reading SPD	commit \| commitdiff \| tree
2020-05-21	Jędrzej Boczar	bios/sdram: add firmware for reading SPD EEPROM	commit \| commitdiff \| tree
2020-04-24	Jędrzej Boczar	bios/sdram: add automatic cdly calibration during write...	commit \| commitdiff \| tree
2020-04-17	Jędrzej Boczar	litex_sim: add option to create SDRAM module from SPD...	commit \| commitdiff \| tree

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