projects
/
riscv-isa-sim.git
/ search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Refactor and fix LR/SC implementation (#217)
2018-07-10
Andrew Waterman
Refactor and fix LR/SC implementation (#217)
commit
|
commitdiff
|
tree
2018-03-22
Andrew Waterman
Implement Hauser misa.C misalignment proposal (#187)
commit
|
commitdiff
|
tree
2018-02-13
Andrew Waterman
Implement cycleh/instreth CSRs for RV32 (#172)
commit
|
commitdiff
|
tree
2017-11-20
Andrew Waterman
Implement priv-1.11 interrupt-priority scheme (#161)
commit
|
commitdiff
|
tree
2017-11-16
Andrew Waterman
Merge pull request #156 from p12nGH/noncontiguous_harts
commit
|
commitdiff
|
tree
2017-10-20
Andrew Waterman
Fix commit-log for Q extension, and for RV32 (#143)
commit
|
commitdiff
|
tree
2017-10-11
Andrew Waterman
Merge pull request #129 from riscv/q-extension
commit
|
commitdiff
|
tree
2015-01-05
Andrew Waterman
canonicalize assembler pseudo-ops
commit
|
commitdiff
|
tree
2015-01-05
Andrew Waterman
Rename riscv-dis to spike-dasm
commit
|
commitdiff
|
tree
2015-01-05
Andrew Waterman
Disassemble jalr x0, x1, 0 as ret
commit
|
commitdiff
|
tree
2015-01-03
Andrew Waterman
Require 4-byte instruction alignment until RVC is reimplemented
commit
|
commitdiff
|
tree
2015-01-03
Andrew Waterman
On misaligned fetch, set EPC to target, not branch...
commit
|
commitdiff
|
tree
2015-01-02
Andrew Waterman
Reduce dependences on auto-generated code
commit
|
commitdiff
|
tree