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soc: Drive uart1_irq to 0 when we don't have UART1
2020-12-17 Paul Mackerrassoc: Drive uart1_irq to 0 when we don't have UART1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-24 Paul Mackerrastests/misc: Add a test for correct CTR and LR updating...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-24 Paul Mackerrasexecute1: Fix forwarding of result when doing delayed...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-21 Paul Mackerrasexecute1: Fix writing LR for bdnzl/bdzl instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-21 Paul Mackerrascore: Implement mtmsr instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-10-05 Paul Mackerrastests/trace: Test trace interrupt vs. FP unavailable...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-10-03 Paul Mackerrasexecute1: Fix bug in trace interrupt vs. ITLB miss
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-12 Paul MackerrasFPU: Do masking after adder rather than on A input
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Decide on mask length a cycle earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Decide on A input selection a cycle earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Add comments specifying the expectation of r.shift...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating multiply-add instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement ftdiv and ftsqrt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fsqrt[s] and add a test for fsqrt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement frsqrte[s] and a test for frsqrte
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for fsel and fcmpu
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fcmpu and fcmpo
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fsel
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fre[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fdiv[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmul[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fadd[s] and fsub[s] and add tests for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmrgew and fmrgow and add tests for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating round-to-integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating convert to integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for frsp
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement the frsp instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating convert from integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmr and related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Test remaining FPSCR-related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement remaining FPSCR-related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for basic FPSCR function and interrupt...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add framework for an FPU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for lfs and stfs instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add support for single-precision FP loads and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests: Add a test for FP loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add support for floating-point loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrastests: Add a test for trace interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrasexecute1: Implement trace interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrasdecode1: Avoid overriding fields of v.decode in decode1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrastests: Add a test for the load-reserve and store-conditional...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrasloadstore1: Generate alignment interrupts for unaligned...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrastests: Add tests for 32-bit and big-endian modes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrascore: Implement 32-bit mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrascore: Implement big-endian mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrastests/mmu: Update to use correct MSR values
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-07 Paul Mackerrascore: Implement BCD Assist instructions addg6s, cdtbcd...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the wait instruction as a no-op
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the reserved no-op instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the addex instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the maddhd, maddhdu and maddld instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the cmpeqb and cmprb instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the bpermd instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the setb instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the mcrxrx instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrascore: Implement the TAR register and the bctar instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasexecute1: Use r.<field> not v.<field> in countzero...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasexecute1: Take an extra cycle for OE=1 multiply instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasmultiplier: Generalize interface to the multiplier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Better expression for store data formatting
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Further tweaks to improve synthesis with...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Ease timing on wishbone data and byte selects
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdecode1: Fix formatting
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Separate address calculation for MMU to...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasloadstore1: Generate busy signal earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Output separate done-without-error and error...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Ease timing on calculation of acks remaining
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-20 Paul Mackerrasdcache: Improve timing of valid/done outputs
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrascore: Don't generate logic for log data when LOG_LENGTH = 0
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrascountzero: Faster algorithm for count leading/trailing...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul MackerrasMMU: Improve timing of done signal back to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Remove dependency of r1.wb.adr/dat/sel on...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Update TLB PLRU one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasloadstore1: Eliminate two_dwords variable
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasexecute1: Ease timing on redirect_nia
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasdcache: Do PLRU update one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-07-14 Paul Mackerrasicache: Do PLRU update one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrasexecute1: Do forwarding of the CR result to the next...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrasexecute1: Add latch to redirect path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerraslogical: Only do output inversion for OP_AND, OP_OR...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-29 Paul Mackerrascore: Implement CFAR register
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasexecute1: Reduce width of the result mux to help timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrascore: Implement a simple branch predictor
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasdecode1: Improve timing for slow SPR decode path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-14 Paul Mackerrasdecode1: Add a stash buffer to the output
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce back-to-back store latency from 3 cycles...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmmu: Take an extra cycle to do TLB invalidations
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce latencies and improve timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdecode: Work out ispr1/ispr2 in parallel with decode...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Reduce busy cycles
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Complete mfspr/mtspr a cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Use a busy signal rather than a stall
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasicache: Improve latencies when reloading cache lines
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Use DSP48 slices for multiplication on Xilinx...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Move selection of result bits into execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Double the dcache and icache sizes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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