| 2018-12-23 |
whitequark | back.rtlil: do not translate empty fragments.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: only translate switch tests once.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: generate: guess file type from extension.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | back.rtlil: fix swapped operands in mux codegen.
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commit | commitdiff | tree |
| 2018-12-23 |
whitequark | cli: new module, for basic design generaton/simulation.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat.genlib.fsm: fix naming for non-Signal LHS.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: flatten hierarchy based on memory accesses...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: factor out _merge_subfragment. NFC.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: implement LHSGroupAnalyzer.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: use nicer names for next_value/next_value_ce...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.mem: allow changing init value after creating memory.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | back.verilog: do not rename internal signals.
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: fix confusing naming for memory port address...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | hdl.ir: fix port propagation between siblings, in the...
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commit | commitdiff | tree |
| 2018-12-22 |
whitequark | compat: do not finalize native submodules twice.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: use more informative signal naming for ports.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: fix port propagation between siblings.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | compat: provide verilog.convert shim.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: do not flatten instances or collect ports from...
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | compat: provide Memory shim.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct...
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: give numeric names to unnamed subfragments...
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: use different naming for array signals.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: add simulation model for memory.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.pysim: fix an issue with too few funclet slots.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: add tests for all error conditions.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transparent...
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.rtlil: more consistent prefixing for subfragment...
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.ir: correctly handle named output and inout ports.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.rtlil: implement memories.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | hdl.mem: implement memories.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.rtlil: explicitly pad constants with zeroes.
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commit | commitdiff | tree |
| 2018-12-21 |
whitequark | back.rtlil: fix translation of Cat.
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commit | commitdiff | tree |
| 2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports.
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commit | commitdiff | tree |
| 2018-12-19 |
whitequark | setup: update pyvcd dependency, for var_type="string".
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | compat: import genlib.record from Migen.
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy...
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts}
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: implement *.
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors.
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: eliminate most dictionary lookups.
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | hdl.ast, hdl.xfrm: various microoptimizations to speed...
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: use arrays instead of dicts for signal...
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: naming. NFC.
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: fix an off-by-1 in add_sync_process().
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: trigger processes waiting on Tick() exactly...
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | back.pysim: continue running simulator processes until...
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commit | commitdiff | tree |
| 2018-12-18 |
whitequark | Travis: cache Yosys installation explicitly.
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters...
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | Travis: build and cache Yosys.
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict.
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | hdl.ast: factor out _MappedKeyDict, _MappedKeySet....
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | back.rtlil: update for Yosys master.
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | back.rtlil: implement Array.
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commit | commitdiff | tree |
| 2018-12-17 |
whitequark | back.rtlil: implement Part.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: handle reset_less domains.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | hdl.dsl: add clock domain support.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | hdl.dsl: cleanup. NFC.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: extract _StatementCompiler. NFC.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: simplify. NFC.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: properly escape strings in attributes.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | README: mention Yosys requirement.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: prepare for Yosys sigspec slicing improvements.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | compat.fhdl.structure: only convert to bool in If/Elif...
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: avoid illegal slices.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: use slicing to match shape when reducing...
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: don't emit a slice if all bits are used.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: reorganize value compiler into LHS/RHS.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.rtlil: fix naming. NFC.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | hdl.xfrm: separate AST traversal from AST identity...
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | compat.fhdl: reexport Array.
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commit | commitdiff | tree |
| 2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | test.sim: generalize assertOperator. NFC.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | back.pysim: add (stub) LHSValueCompiler.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | back.pysim: implement Part.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | examples: rename clkdiv/ctrl to ctr/ctr_ce.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | doc: update COMPAT_SUMMARY.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | back.pysim: implement ArrayProxy.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | hdl.ast: implement Array and ArrayProxy.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Lower Python version requirement to 3.6.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | hdl: appropriately rename tests. NFC.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | hdl.ast: improve ClockSignal, ResetSignal documentation.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Move star imports to make `from nmigen import *` usable.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | doc: fix some Markdown awkwardness.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | doc: update COMPAT_SUMMARY to reflect actual status.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Determine Migen's API surface and document compatibility...
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | pyback.sim: test Slice, Cat, Repl.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ast: refactor Operator.shape(). NFC.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Consistently use '{!r}' in and only in TypeError messages.
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ir: fix incorrect uses of positive to say non...
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commit | commitdiff | tree |
| 2018-12-15 |
whitequark | compat.fhdl.structure: handle If/Elif with multi-bit...
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commit | commitdiff | tree |
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