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2022-04-25	Miodrag Milanović	Merge pull request #3289 from YosysHQ/micko/sim_improve	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Match $anyseq input if connected to public wire	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Treat $anyseq as input from FST	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Ignore change on last edge	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Last sample from input does not represent change	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	latches are always set to zero	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	If not multiclock, output only on clock edges	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Set init state for all wires from FST and set past	commit \| commitdiff \| tree
2022-04-22	Miodrag Milanovic	Fix multiclock for btor2 witness	commit \| commitdiff \| tree
2022-04-18	Miodrag Milanović	Merge pull request #3280 from YosysHQ/micko/fix_readaiw	commit \| commitdiff \| tree
2022-04-18	Miodrag Milanovic	Update abc	commit \| commitdiff \| tree
2022-04-18	Miodrag Milanovic	verific: allow memories to be inferred in loops (vhdl)	commit \| commitdiff \| tree
2022-04-18	Miodrag Milanović	Merge pull request #3282 from nakengelhardt/verific_loop_rams	commit \| commitdiff \| tree
2022-04-15	Miodrag Milanovic	Fix reading aiw from other solvers	commit \| commitdiff \| tree
2022-04-08	Miodrag Milanović	Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix	commit \| commitdiff \| tree
2022-04-08	Miodrag Milanovic	Use wrap_async_control_gate if ff is fine	commit \| commitdiff \| tree
2022-04-08	Miodrag Milanović	Merge pull request #3273 from modwizcode/fix-build	commit \| commitdiff \| tree
2022-04-05	Miodrag Milanovic	Reorder steps in -auto-top to fix synth command, fixes...	commit \| commitdiff \| tree
2022-04-05	Miodrag Milanovic	Next dev cycle	commit \| commitdiff \| tree
2022-04-05	Miodrag Milanovic	Release version 0.16	commit \| commitdiff \| tree
2022-04-04	Miodrag Milanovic	Update CHANGELOG and manual	commit \| commitdiff \| tree
2022-04-04	Miodrag Milanović	Merge pull request #3265 from YosysHQ/micko/sim_improvements	commit \| commitdiff \| tree
2022-04-02	Miodrag Milanovic	past_ad initial value setting	commit \| commitdiff \| tree
2022-04-02	Miodrag Milanovic	setInitState can be only one altering values	commit \| commitdiff \| tree
2022-04-02	Miodrag Milanovic	Set past_d value for init state	commit \| commitdiff \| tree
2022-04-01	Miodrag Milanović	Merge pull request #3263 from YosysHQ/micko/clk2ff_init	commit \| commitdiff \| tree
2022-04-01	Miodrag Milanovic	Set init values for wrapped async control signals	commit \| commitdiff \| tree
2022-04-01	Miodrag Milanović	Merge pull request #3262 from YosysHQ/micko/verific_hiernet	commit \| commitdiff \| tree
2022-04-01	Miodrag Milanovic	Preserve internal wires for external nets	commit \| commitdiff \| tree
2022-03-31	Miodrag Milanović	Merge pull request #3256 from YosysHQ/micko/aiw_multiclock	commit \| commitdiff \| tree
2022-03-31	Miodrag Milanovic	Support memories in aiw and multiclock	commit \| commitdiff \| tree
2022-03-30	Miodrag Milanović	Merge pull request #3259 from YosysHQ/micko/verific_valgrind	commit \| commitdiff \| tree
2022-03-30	Miodrag Milanovic	Fix valgrind tests when using verific	commit \| commitdiff \| tree
2022-03-30	Miodrag Milanović	Merge pull request #3260 from YosysHQ/micko/proper_scopename	commit \| commitdiff \| tree
2022-03-30	Miodrag Milanovic	Proper scope naming from FST	commit \| commitdiff \| tree
2022-03-30	Miodrag Milanović	Merge pull request #3250 from YosysHQ/micko/verific_consistent	commit \| commitdiff \| tree
2022-03-29	Miodrag Milanović	Merge pull request #3258 from jix/fix-no-assertions	commit \| commitdiff \| tree
2022-03-28	Miodrag Milanović	Update URL to zlib	commit \| commitdiff \| tree
2022-03-26	Miodrag Milanovic	Properly mark modules imported	commit \| commitdiff \| tree
2022-03-25	Miodrag Milanović	Merge pull request #3249 from YosysHQ/micko/no_startoffset	commit \| commitdiff \| tree
2022-03-25	Miodrag Milanovic	Import verific netlist in consistent order	commit \| commitdiff \| tree
2022-03-25	Miodrag Milanovic	Add -no-startoffset option to write_aiger	commit \| commitdiff \| tree
2022-03-24	Miodrag Milanović	Merge pull request #3243 from nakengelhardt/fix_aiw_comment	commit \| commitdiff \| tree
2022-03-22	Miodrag Milanovic	Update abc with latest fix	commit \| commitdiff \| tree
2022-03-22	Miodrag Milanovic	Proper SigBit forming in sim	commit \| commitdiff \| tree
2022-03-22	Miodrag Milanovic	Proper SigBit forming in sim	commit \| commitdiff \| tree
2022-03-18	Miodrag Milanovic	More verbose warnings	commit \| commitdiff \| tree
2022-03-17	Miodrag Milanović	Merge pull request #3236 from YosysHQ/micko/tb_initial	commit \| commitdiff \| tree
2022-03-16	Miodrag Milanovic	Recognize registers and set initial state for them...	commit \| commitdiff \| tree
2022-03-16	Miodrag Milanovic	Update sim help message.	commit \| commitdiff \| tree
2022-03-14	Miodrag Milanović	Merge pull request #3232 from YosysHQ/micko/fst2tb	commit \| commitdiff \| tree
2022-03-14	Miodrag Milanovic	Added fst2tb pass for generating testbench	commit \| commitdiff \| tree
2022-03-14	Miodrag Milanovic	Proper example code	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanović	Merge pull request #3229 from YosysHQ/micko/sim_date	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanović	Merge pull request #3222 from zachjs/prune-linux-ci	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanović	Merge pull request #3228 from YosysHQ/micko/disable_tests	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanovic	Add date parameter to enable full date/time and version...	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanović	Merge pull request #3226 from YosysHQ/micko/btor2witness	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanovic	FstData already do conversion to VCD	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanovic	Support cell name in btor witness file	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanovic	handle state names of $anyconst and $anyseq	commit \| commitdiff \| tree
2022-03-11	Miodrag Milanovic	Proper write of memory data	commit \| commitdiff \| tree
2022-03-10	Miodrag Milanovic	Disable tests on most of platforms	commit \| commitdiff \| tree
2022-03-09	Miodrag Milanovic	Start work on memory init	commit \| commitdiff \| tree
2022-03-09	Miodrag Milanovic	Fixes and error check	commit \| commitdiff \| tree
2022-03-07	Miodrag Milanovic	cleanup	commit \| commitdiff \| tree
2022-03-07	Miodrag Milanovic	Error checks for aiger witness	commit \| commitdiff \| tree
2022-03-07	Miodrag Milanovic	btor2 witness co-simulation	commit \| commitdiff \| tree
2022-03-07	Miodrag Milanović	Merge pull request #3210 from rqou/json-signed	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanović	Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanović	Merge pull request #3206 from YosysHQ/micko/quote_remove	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanović	Merge pull request #3207 from nakengelhardt/json_escape_quotes	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanovic	Next dev cycle	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanovic	Release version 0.15	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanovic	Update ABC	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanovic	Update documentation	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanović	Merge pull request #3219 from YosysHQ/micko/quick_vcd	commit \| commitdiff \| tree
2022-03-04	Miodrag Milanović	Merge pull request #3220 from YosysHQ/claire/simstuff	commit \| commitdiff \| tree
2022-03-02	Miodrag Milanovic	Add option to ignore X only signals in output	commit \| commitdiff \| tree
2022-03-02	Miodrag Milanovic	Write simulation files after simulation is performed	commit \| commitdiff \| tree
2022-03-02	Miodrag Milanovic	Update CHANGELOG	commit \| commitdiff \| tree
2022-03-02	Miodrag Milanovic	Cleanup	commit \| commitdiff \| tree
2022-02-28	Miodrag Milanovic	Refactor sim output writers	commit \| commitdiff \| tree
2022-02-28	Miodrag Milanovic	Quick fix	commit \| commitdiff \| tree
2022-02-28	Miodrag Milanovic	VCD reader support by using external tool	commit \| commitdiff \| tree
2022-02-28	Miodrag Milanović	Merge pull request #3216 from YosysHQ/claire/simstuff	commit \| commitdiff \| tree
2022-02-27	Miodrag Milanovic	Support extended aiw format	commit \| commitdiff \| tree
2022-02-25	Miodrag Milanovic	Fix for last clock edge data	commit \| commitdiff \| tree
2022-02-21	Miodrag Milanović	Merge pull request #3203 from YosysHQ/micko/sim_ff	commit \| commitdiff \| tree
2022-02-21	Miodrag Milanovic	Fix handling of ce_over_srst	commit \| commitdiff \| tree
2022-02-18	Miodrag Milanovic	Changed error message	commit \| commitdiff \| tree
2022-02-18	Miodrag Milanovic	Added AIGER witness file co simulation	commit \| commitdiff \| tree
2022-02-18	Miodrag Milanovic	simplify logic of handling flip-flops and latches	commit \| commitdiff \| tree
2022-02-17	Miodrag Milanovic	Review cleanup	commit \| commitdiff \| tree
2022-02-16	Miodrag Milanovic	Remove quotes if any from attribute	commit \| commitdiff \| tree
2022-02-16	Miodrag Milanovic	test dlatchsr and adlatch	commit \| commitdiff \| tree
2022-02-16	Miodrag Milanovic	Added test cases	commit \| commitdiff \| tree
2022-02-16	Miodrag Milanovic	Add support for various ff/latch cells simulation	commit \| commitdiff \| tree
2022-02-15	Miodrag Milanović	Merge pull request #3204 from YosysHQ/claire/update-abc	commit \| commitdiff \| tree
2022-02-15	Miodrag Milanovic	Bump ABC version	commit \| commitdiff \| tree
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