git.libre-soc.org Git - nmigen.git/search

2020-11-06	awygle	hdl.rec: migrate Record from UserValue to ValueCastable.	commit \| commitdiff \| tree
2020-11-06	awygle	hdl.ast: implement ValueCastable.	commit \| commitdiff \| tree
2020-11-02	David Lattimore	vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC...	commit \| commitdiff \| tree
2020-10-27	Ben Newhouse	setup: link to latest docs if VCS information is not...	commit \| commitdiff \| tree
2020-10-24	anuejn	lib.fifo.AsyncFIFO: fix incorrect latency of r_level.	commit \| commitdiff \| tree
2020-10-22	anuejn	tests: make spec directory name unique per test method.	commit \| commitdiff \| tree
2020-10-15	Jan Kowalewski	vendor.quicklogic: new platform.	commit \| commitdiff \| tree
2020-08-29	William D. Jones	vendor.lattice_{ecp5,machxo_2_3l}: explain how to set...	commit \| commitdiff \| tree
2020-08-26	William D. Jones	build.run: implement SSH remote builds using Paramiko.	commit \| commitdiff \| tree
2020-08-15	awygle	lib.fifo: add `r_level` and `w_level` to all FIFOs	commit \| commitdiff \| tree
2020-07-30	Adam Greig	hdl.mem: cast reset value for transparent read ports...	commit \| commitdiff \| tree
2020-07-28	Jean THOMAS	nmigen.lib.scheduler: add RoundRobin.	commit \| commitdiff \| tree
2020-07-28	Jacob Graves	tests: fix remove unnecessary workaround for some unittest...	commit \| commitdiff \| tree
2020-07-23	Jean THOMAS	vendor.lattice_ecp5: add missing differential IO types.	commit \| commitdiff \| tree
2020-07-13	Jacob Lifshay	sim.pysim: write the next, not curr signal value to...	commit \| commitdiff \| tree
2020-07-07	awygle	hdl.ast: don't inherit Shape from NamedTuple.	commit \| commitdiff \| tree
2020-06-23	Alan Green	_yosys: handle unparseable versions	commit \| commitdiff \| tree
2020-06-21	Gwenhael Goavec...	vendor.lattice_machxo*: add MachXO3L support.	commit \| commitdiff \| tree
2020-06-06	Adam Greig	hdl.xfrm: preserve allow_reset_less when transforming...	commit \| commitdiff \| tree
2020-06-05	Shawn Anastasio	hdl.rec: preserve shapes when constructing a layout.	commit \| commitdiff \| tree
2020-05-08	Gwenhael Goavec...	vendor.lattice_machxo2: generate binary bitstreams.	commit \| commitdiff \| tree
2020-04-24	awygle	lib.fifo: add r_rst output for AsyncFIFO{,Buffered}.	commit \| commitdiff \| tree
2020-04-24	awygle	hdl.ir: typecheck `convert(ports=)` more carefully.	commit \| commitdiff \| tree
2020-04-23	Teguh Hofstee	back.verilog: add workaround for evaluation Verific...	commit \| commitdiff \| tree
2020-04-22	Teguh Hofstee	back.verilog: make Yosys version check compatible with...	commit \| commitdiff \| tree
2020-04-16	anuejn	hdl.rec: make Record inherit from UserValue.	commit \| commitdiff \| tree
2020-04-13	Dan Ravensloft	hdl.ast: add Value.{rotate_left,rotate_right}.	commit \| commitdiff \| tree
2020-03-20	WRansohoff	vendor.lattice_ice40: add support for SB_[LH]FOSC as...	commit \| commitdiff \| tree
2020-03-15	Stuart Olsen	back.pysim: implement modulus operator.	commit \| commitdiff \| tree
2020-03-14	awygle	Correctly handle resets in AsyncFIFO.	commit \| commitdiff \| tree
2020-03-08	awygle	lib.cdc: extract AsyncFFSynchronizer.	commit \| commitdiff \| tree
2020-02-16	awygle	nmigen.compat.genlib.cdc: add PulseSynchronizer.	commit \| commitdiff \| tree
2020-02-16	awygle	nmigen.lib.cdc: port PulseSynchronizer.	commit \| commitdiff \| tree
2020-01-27	whitequark	Update README.	commit \| commitdiff \| tree

RSS Atom