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Release version 0.16
2022-04-05
Miodrag Milanovic
Release version 0.16
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2022-04-04
Miodrag Milanovic
Update CHANGELOG and manual
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2022-04-02
Miodrag Milanovic
past_ad initial value setting
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2022-04-02
Miodrag Milanovic
setInitState can be only one altering values
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2022-04-02
Miodrag Milanovic
Set past_d value for init state
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2022-04-01
Miodrag Milanovic
Set init values for wrapped async control signals
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2022-04-01
Miodrag Milanovic
Preserve internal wires for external nets
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2022-03-31
Miodrag Milanovic
Support memories in aiw and multiclock
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2022-03-30
Miodrag Milanovic
Fix valgrind tests when using verific
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2022-03-30
Miodrag Milanovic
Proper scope naming from FST
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2022-03-26
Miodrag Milanovic
Properly mark modules imported
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2022-03-25
Miodrag Milanovic
Import verific netlist in consistent order
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2022-03-25
Miodrag Milanovic
Add -no-startoffset option to write_aiger
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2022-03-22
Miodrag Milanovic
Update abc with latest fix
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-22
Miodrag Milanovic
Proper SigBit forming in sim
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2022-03-18
Miodrag Milanovic
More verbose warnings
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2022-03-16
Miodrag Milanovic
Recognize registers and set initial state for them...
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2022-03-16
Miodrag Milanovic
Update sim help message.
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2022-03-14
Miodrag Milanovic
Added fst2tb pass for generating testbench
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2022-03-14
Miodrag Milanovic
Proper example code
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2022-03-11
Miodrag Milanovic
Add date parameter to enable full date/time and version...
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2022-03-11
Miodrag Milanovic
FstData already do conversion to VCD
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2022-03-11
Miodrag Milanovic
Support cell name in btor witness file
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2022-03-11
Miodrag Milanovic
handle state names of $anyconst and $anyseq
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2022-03-11
Miodrag Milanovic
Proper write of memory data
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2022-03-10
Miodrag Milanovic
Disable tests on most of platforms
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2022-03-09
Miodrag Milanovic
Start work on memory init
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2022-03-09
Miodrag Milanovic
Fixes and error check
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2022-03-07
Miodrag Milanovic
cleanup
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2022-03-07
Miodrag Milanovic
Error checks for aiger witness
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2022-03-07
Miodrag Milanovic
btor2 witness co-simulation
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2022-03-04
Miodrag Milanovic
Next dev cycle
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2022-03-04
Miodrag Milanovic
Release version 0.15
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2022-03-04
Miodrag Milanovic
Update ABC
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2022-03-04
Miodrag Milanovic
Update documentation
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2022-03-02
Miodrag Milanovic
Add option to ignore X only signals in output
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2022-03-02
Miodrag Milanovic
Write simulation files after simulation is performed
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2022-03-02
Miodrag Milanovic
Update CHANGELOG
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2022-03-02
Miodrag Milanovic
Cleanup
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2022-02-28
Miodrag Milanovic
Refactor sim output writers
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2022-02-28
Miodrag Milanovic
Quick fix
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2022-02-28
Miodrag Milanovic
VCD reader support by using external tool
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2022-02-27
Miodrag Milanovic
Support extended aiw format
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2022-02-25
Miodrag Milanovic
Fix for last clock edge data
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2022-02-21
Miodrag Milanovic
Fix handling of ce_over_srst
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2022-02-18
Miodrag Milanovic
Changed error message
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2022-02-18
Miodrag Milanovic
Added AIGER witness file co simulation
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2022-02-18
Miodrag Milanovic
simplify logic of handling flip-flops and latches
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2022-02-17
Miodrag Milanovic
Review cleanup
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2022-02-16
Miodrag Milanovic
Remove quotes if any from attribute
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2022-02-16
Miodrag Milanovic
test dlatchsr and adlatch
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2022-02-16
Miodrag Milanovic
Added test cases
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2022-02-16
Miodrag Milanovic
Add support for various ff/latch cells simulation
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2022-02-15
Miodrag Milanovic
Bump ABC version
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2022-02-09
Miodrag Milanovic
Add ability to override verilog mode for verific -f...
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2022-02-07
Miodrag Milanovic
Next dev cycle
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2022-02-07
Miodrag Milanovic
Release version 0.14
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2022-02-07
Miodrag Milanovic
Update CHANGELOG and manual
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2022-02-04
Miodrag Milanovic
Error detection for co-simulation
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2022-02-04
Miodrag Milanovic
bug fix and cleanups
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2022-02-02
Miodrag Milanovic
Use bmux for NTO1MUX
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2022-02-02
Miodrag Milanovic
Add test cases for co-simulation
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2022-02-02
Miodrag Milanovic
Fix Visual Studio build
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2022-02-02
Miodrag Milanovic
respect hide_internal flag
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2022-02-02
Miodrag Milanovic
unify cycles counting and cleanup
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2022-02-02
Miodrag Milanovic
added stimulus mode and param check
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2022-01-31
Miodrag Milanovic
error when no signal found
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2022-01-31
Miodrag Milanovic
Cleanup
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2022-01-31
Miodrag Milanovic
Compare bits when not all are defined
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2022-01-31
Miodrag Milanovic
Cleanup
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2022-01-31
Miodrag Milanovic
message update
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2022-01-31
Miodrag Milanovic
Display simulation time data
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2022-01-31
Miodrag Milanovic
Use edges when explicit
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2022-01-31
Miodrag Milanovic
Updating initial state and checks
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2022-01-31
Miodrag Milanovic
Fix scope
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2022-01-28
Miodrag Milanovic
check if stop before start
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2022-01-28
Miodrag Milanovic
set initial state, only flip-flops
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2022-01-28
Miodrag Milanovic
ignore not found private signals
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2022-01-28
Miodrag Milanovic
preserve VCD mangled names
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2022-01-28
Miodrag Milanovic
detect edges even when x
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2022-01-28
Miodrag Milanovic
recursive check
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2022-01-28
Miodrag Milanovic
cleanup
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2022-01-28
Miodrag Milanovic
Do actual compare
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2022-01-28
Miodrag Milanovic
Fix for limit_range_end when not writing vcd
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2022-01-28
Miodrag Milanovic
Add more options and time handling
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2022-01-26
Miodrag Milanovic
update version
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2022-01-26
Miodrag Milanovic
Display values of outputs
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2022-01-26
Miodrag Milanovic
Fix tabs/spaces
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2022-01-26
Miodrag Milanovic
Check if stimulated
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2022-01-26
Miodrag Milanovic
Read fst and use data to set inputs
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2022-01-26
Miodrag Milanovic
Add fstdata helper class
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2022-01-26
Miodrag Milanovic
Cleanup of config to support platforms
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2022-01-26
Miodrag Milanovic
Add ability to write to FST file
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2022-01-25
Miodrag Milanovic
Add FST library
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2022-01-19
Miodrag Milanovic
Removed dbits 8 since 9 will always be picked
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2022-01-11
Miodrag Milanovic
Forgot one
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2022-01-11
Miodrag Milanovic
Change url to https
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2022-01-11
Miodrag Milanovic
Next dev cycle
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2022-01-11
Miodrag Milanovic
Release version 0.13
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